| Line 1... |
Line 1... |
//
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//
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// eco32.v -- ECO32 top-level description
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// eco32.v -- ECO32 top-level description
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//
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//
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`timescale 1ns/10ps
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`default_nettype none
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module eco32(clk_in,
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module eco32(clk_in,
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reset_inout_n,
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rst_inout_n,
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sdram_clk,
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sdram_clk,
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sdram_fb,
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sdram_fb,
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sdram_cke,
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sdram_cke,
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sdram_cs_n,
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sdram_cs_n,
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sdram_ras_n,
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sdram_ras_n,
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| Line 57... |
Line 61... |
sw2_n,
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sw2_n,
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sw3_n);
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sw3_n);
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// clock and reset
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// clock and reset
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input clk_in;
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input clk_in;
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inout reset_inout_n;
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inout rst_inout_n;
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// SDRAM
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// SDRAM
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output sdram_clk;
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output sdram_clk;
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input sdram_fb;
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input sdram_fb;
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output sdram_cke;
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output sdram_cke;
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output sdram_cs_n;
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output sdram_cs_n;
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| Line 124... |
Line 128... |
input sw1_4;
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input sw1_4;
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input sw2_n;
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input sw2_n;
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input sw3_n;
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input sw3_n;
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// clk_rst
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// clk_rst
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wire clk;
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wire clk; // system clock
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wire clk_ok;
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wire clk_ok; // clock is stable
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wire reset;
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wire rst; // system reset
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// cpu
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// cpu
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wire cpu_en;
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wire bus_stb; // bus strobe
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wire cpu_wr;
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wire bus_we; // bus write enable
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wire [1:0] cpu_size;
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wire [31:2] bus_addr; // bus address (word address)
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wire [31:0] cpu_addr;
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wire [31:0] bus_din; // bus data input, for reads
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wire [31:0] cpu_data_in;
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wire [31:0] bus_dout; // bus data output, for writes
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wire [31:0] cpu_data_out;
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wire bus_ack; // bus acknowledge
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wire cpu_wt;
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wire [15:0] bus_irq; // bus interrupt requests
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wire [15:0] cpu_irq;
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// ram
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// ram
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wire ram_en;
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wire ram_stb; // ram strobe
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wire ram_wr;
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wire [31:0] ram_dout; // ram data output
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wire [1:0] ram_size;
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wire ram_ack; // ram acknowledge
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wire [24:0] ram_addr;
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wire [31:0] ram_data_in;
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wire [31:0] ram_data_out;
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wire ram_wt;
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// rom
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// rom
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wire rom_en;
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wire rom_stb; // rom strobe
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wire rom_wr;
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wire [31:0] rom_dout; // rom data output
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wire [1:0] rom_size;
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wire rom_ack; // rom acknowledge
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wire [20:0] rom_addr;
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// i/o
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wire [31:0] rom_data_out;
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wire i_o_stb; // i/o strobe
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wire rom_wt;
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// tmr0
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// tmr0
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wire tmr0_en;
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wire tmr0_stb; // tmr 0 strobe
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wire tmr0_wr;
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wire [31:0] tmr0_dout; // tmr 0 data output
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wire [3:2] tmr0_addr;
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wire tmr0_ack; // tmr 0 acknowledge
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wire [31:0] tmr0_data_in;
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wire tmr0_irq; // tmr 0 interrupt request
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wire [31:0] tmr0_data_out;
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wire tmr0_wt;
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wire tmr0_irq;
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// tmr1
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// tmr1
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wire tmr1_en;
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wire tmr1_stb; // tmr 1 strobe
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wire tmr1_wr;
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wire [31:0] tmr1_dout; // tmr 1 data output
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wire [3:2] tmr1_addr;
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wire tmr1_ack; // tmr 1 acknowledge
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wire [31:0] tmr1_data_in;
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wire tmr1_irq; // tmr 1 interrupt request
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wire [31:0] tmr1_data_out;
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wire tmr1_wt;
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wire tmr1_irq;
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// dsp
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// dsp
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wire dsp_en;
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wire dsp_stb; // dsp strobe
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wire dsp_wr;
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wire [15:0] dsp_dout; // dsp data output
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wire [13:2] dsp_addr;
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wire dsp_ack; // dsp acknowledge
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wire [15:0] dsp_data_in;
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wire [15:0] dsp_data_out;
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wire dsp_wt;
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// kbd
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// kbd
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wire kbd_en;
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wire kbd_stb; // kbd strobe
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wire kbd_wr;
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wire [7:0] kbd_dout; // kbd data output
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wire kbd_addr;
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wire kbd_ack; // kbd acknowledge
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wire [7:0] kbd_data_in;
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wire kbd_irq; // kbd interrupt request
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wire [7:0] kbd_data_out;
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wire kbd_wt;
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wire kbd_irq;
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// ser0
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// ser0
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wire ser0_en;
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wire ser0_stb; // ser 0 strobe
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wire ser0_wr;
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wire [7:0] ser0_dout; // ser 0 data output
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wire [3:2] ser0_addr;
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wire ser0_ack; // ser 0 acknowledge
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wire [7:0] ser0_data_in;
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wire ser0_irq_r; // ser 0 rcv interrupt request
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wire [7:0] ser0_data_out;
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wire ser0_irq_t; // ser 0 xmt interrupt request
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wire ser0_wt;
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wire ser0_irq_r;
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wire ser0_irq_t;
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// ser1
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// ser1
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wire ser1_en;
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wire ser1_stb; // ser 1 strobe
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wire ser1_wr;
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wire [7:0] ser1_dout; // ser 1 data output
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wire [3:2] ser1_addr;
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wire ser1_ack; // ser 1 acknowledge
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wire [7:0] ser1_data_in;
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wire ser1_irq_r; // ser 1 rcv interrupt request
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wire [7:0] ser1_data_out;
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wire ser1_irq_t; // ser 1 xmt interrupt request
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wire ser1_wt;
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wire ser1_irq_r;
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wire ser1_irq_t;
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// dsk
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// dsk
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wire dsk_en;
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wire dsk_stb; // dsk strobe
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wire dsk_wr;
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wire [31:0] dsk_dout; // dsk data output
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wire [19:2] dsk_addr;
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wire dsk_ack; // dsk acknowledge
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wire [31:0] dsk_data_in;
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wire dsk_irq; // dsk interrupt request
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wire [31:0] dsk_data_out;
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wire dsk_wt;
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wire dsk_irq;
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// fms
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// fms
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wire fms_en;
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wire fms_stb; // fms strobe
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wire fms_wr;
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wire [31:0] fms_dout; // fms data output
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wire [11:2] fms_addr;
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wire fms_ack; // fms acknowledge
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wire [31:0] fms_data_in;
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wire [31:0] fms_data_out;
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wire fms_wt;
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// dac
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// dac
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wire [15:0] dac_sample_l;
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wire [15:0] dac_sample_l; // dac sample value, left
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wire [15:0] dac_sample_r;
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wire [15:0] dac_sample_r; // dac sample value, right
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wire dac_next;
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wire dac_next; // dac next sample request
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// bio
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// bio
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wire bio_en;
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wire bio_stb; // bio strobe
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wire bio_wr;
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wire [31:0] bio_dout; // bio data output
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wire bio_addr;
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wire bio_ack; // bio acknowledge
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wire [31:0] bio_data_in;
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wire [31:0] bio_data_out;
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//--------------------------------------
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wire bio_wt;
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// module instances
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//--------------------------------------
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clk_rst clk_rst1(
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clk_rst clk_rst_1(
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.clk_in(clk_in),
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.clk_in(clk_in),
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.reset_inout_n(reset_inout_n),
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.rst_inout_n(rst_inout_n),
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.sdram_clk(sdram_clk),
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.sdram_clk(sdram_clk),
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.sdram_fb(sdram_fb),
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.sdram_fb(sdram_fb),
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.clk(clk),
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.clk(clk),
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.clk_ok(clk_ok),
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.clk_ok(clk_ok),
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.reset(reset)
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.rst(rst)
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);
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);
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busctrl busctrl1(
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cpu cpu_1(
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// cpu
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.clk(clk),
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.cpu_en(cpu_en),
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.rst(rst),
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.cpu_wr(cpu_wr),
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.bus_stb(bus_stb),
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.cpu_size(cpu_size[1:0]),
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.bus_we(bus_we),
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.cpu_addr(cpu_addr[31:0]),
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.bus_addr(bus_addr[31:2]),
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.cpu_data_in(cpu_data_in[31:0]),
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.bus_din(bus_din[31:0]),
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.cpu_data_out(cpu_data_out[31:0]),
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.bus_dout(bus_dout[31:0]),
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.cpu_wt(cpu_wt),
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.bus_ack(bus_ack),
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// ram
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.bus_irq(bus_irq[15:0])
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.ram_en(ram_en),
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);
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.ram_wr(ram_wr),
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.ram_size(ram_size[1:0]),
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.ram_addr(ram_addr[24:0]),
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.ram_data_in(ram_data_in[31:0]),
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.ram_data_out(ram_data_out[31:0]),
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.ram_wt(ram_wt),
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// rom
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.rom_en(rom_en),
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.rom_wr(rom_wr),
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.rom_size(rom_size[1:0]),
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.rom_addr(rom_addr[20:0]),
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.rom_data_out(rom_data_out[31:0]),
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.rom_wt(rom_wt),
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// tmr0
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.tmr0_en(tmr0_en),
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.tmr0_wr(tmr0_wr),
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.tmr0_addr(tmr0_addr[3:2]),
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.tmr0_data_in(tmr0_data_in[31:0]),
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.tmr0_data_out(tmr0_data_out[31:0]),
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.tmr0_wt(tmr0_wt),
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// tmr1
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.tmr1_en(tmr1_en),
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.tmr1_wr(tmr1_wr),
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.tmr1_addr(tmr1_addr[3:2]),
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.tmr1_data_in(tmr1_data_in[31:0]),
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.tmr1_data_out(tmr1_data_out[31:0]),
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.tmr1_wt(tmr1_wt),
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// dsp
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.dsp_en(dsp_en),
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.dsp_wr(dsp_wr),
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.dsp_addr(dsp_addr[13:2]),
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.dsp_data_in(dsp_data_in[15:0]),
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.dsp_data_out(dsp_data_out[15:0]),
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.dsp_wt(dsp_wt),
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// kbd
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.kbd_en(kbd_en),
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.kbd_wr(kbd_wr),
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.kbd_addr(kbd_addr),
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.kbd_data_in(kbd_data_in[7:0]),
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.kbd_data_out(kbd_data_out[7:0]),
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.kbd_wt(kbd_wt),
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// ser0
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.ser0_en(ser0_en),
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.ser0_wr(ser0_wr),
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.ser0_addr(ser0_addr[3:2]),
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.ser0_data_in(ser0_data_in[7:0]),
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.ser0_data_out(ser0_data_out[7:0]),
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.ser0_wt(ser0_wt),
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// ser1
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.ser1_en(ser1_en),
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.ser1_wr(ser1_wr),
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.ser1_addr(ser1_addr[3:2]),
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.ser1_data_in(ser1_data_in[7:0]),
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.ser1_data_out(ser1_data_out[7:0]),
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.ser1_wt(ser1_wt),
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// dsk
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.dsk_en(dsk_en),
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.dsk_wr(dsk_wr),
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.dsk_addr(dsk_addr[19:2]),
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.dsk_data_in(dsk_data_in[31:0]),
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.dsk_data_out(dsk_data_out[31:0]),
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.dsk_wt(dsk_wt),
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// fms
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.fms_en(fms_en),
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.fms_wr(fms_wr),
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.fms_addr(fms_addr[11:2]),
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.fms_data_in(fms_data_in[31:0]),
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.fms_data_out(fms_data_out[31:0]),
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.fms_wt(fms_wt),
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// bio
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.bio_en(bio_en),
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.bio_wr(bio_wr),
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.bio_addr(bio_addr),
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.bio_data_in(bio_data_in[31:0]),
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.bio_data_out(bio_data_out[31:0]),
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.bio_wt(bio_wt)
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);
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cpu cpu1(
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.clk(clk),
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.reset(reset),
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.bus_en(cpu_en),
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.bus_wr(cpu_wr),
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.bus_size(cpu_size[1:0]),
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.bus_addr(cpu_addr[31:0]),
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.bus_data_in(cpu_data_in[31:0]),
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.bus_data_out(cpu_data_out[31:0]),
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.bus_wt(cpu_wt),
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.irq(cpu_irq[15:0])
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);
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assign cpu_irq[15] = tmr1_irq;
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assign cpu_irq[14] = tmr0_irq;
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assign cpu_irq[13] = 1'b0;
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assign cpu_irq[12] = 1'b0;
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assign cpu_irq[11] = 1'b0;
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assign cpu_irq[10] = 1'b0;
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assign cpu_irq[ 9] = 1'b0;
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assign cpu_irq[ 8] = dsk_irq;
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assign cpu_irq[ 7] = 1'b0;
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assign cpu_irq[ 6] = 1'b0;
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assign cpu_irq[ 5] = 1'b0;
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assign cpu_irq[ 4] = kbd_irq;
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assign cpu_irq[ 3] = ser1_irq_r;
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assign cpu_irq[ 2] = ser1_irq_t;
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assign cpu_irq[ 1] = ser0_irq_r;
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assign cpu_irq[ 0] = ser0_irq_t;
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ram ram1(
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ram ram_1(
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.clk(clk),
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.clk(clk),
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.clk_ok(clk_ok),
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.clk_ok(clk_ok),
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.reset(reset),
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.rst(rst),
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.en(ram_en),
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.stb(ram_stb),
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.wr(ram_wr),
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.we(bus_we),
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.size(ram_size[1:0]),
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.addr(bus_addr[24:2]),
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.addr(ram_addr[24:0]),
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.data_in(bus_dout[31:0]),
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.data_in(ram_data_in[31:0]),
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.data_out(ram_dout[31:0]),
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.data_out(ram_data_out[31:0]),
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.ack(ram_ack),
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.wt(ram_wt),
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.sdram_cke(sdram_cke),
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.sdram_cke(sdram_cke),
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.sdram_cs_n(sdram_cs_n),
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.sdram_cs_n(sdram_cs_n),
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.sdram_ras_n(sdram_ras_n),
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.sdram_ras_n(sdram_ras_n),
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.sdram_cas_n(sdram_cas_n),
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.sdram_cas_n(sdram_cas_n),
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.sdram_we_n(sdram_we_n),
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.sdram_we_n(sdram_we_n),
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| Line 379... |
Line 246... |
.sdram_udqm(sdram_udqm),
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.sdram_udqm(sdram_udqm),
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.sdram_ldqm(sdram_ldqm),
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.sdram_ldqm(sdram_ldqm),
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.sdram_dq(sdram_dq[15:0])
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.sdram_dq(sdram_dq[15:0])
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);
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);
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rom rom1(
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rom rom_1(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.rst(rst),
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.en(rom_en),
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.stb(rom_stb),
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.wr(rom_wr),
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.we(bus_we),
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.size(rom_size[1:0]),
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.addr(bus_addr[20:2]),
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.addr(rom_addr[20:0]),
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.data_out(rom_dout[31:0]),
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.data_out(rom_data_out[31:0]),
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.ack(rom_ack),
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.wt(rom_wt),
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.ce_n(flash_ce_n),
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.ce_n(flash_ce_n),
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.oe_n(flash_oe_n),
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.oe_n(flash_oe_n),
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.we_n(flash_we_n),
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.we_n(flash_we_n),
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.rst_n(flash_rst_n),
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.rst_n(flash_rst_n),
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.byte_n(flash_byte_n),
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.byte_n(flash_byte_n),
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.a(flash_a[19:0]),
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.a(flash_a[19:0]),
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.d(flash_d[15:0])
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.d(flash_d[15:0])
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);
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);
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tmr tmr1_0(
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tmr tmr_1(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.rst(rst),
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.en(tmr0_en),
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.stb(tmr0_stb),
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.wr(tmr0_wr),
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.we(bus_we),
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.addr(tmr0_addr[3:2]),
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.addr(bus_addr[3:2]),
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.data_in(tmr0_data_in[31:0]),
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.data_in(bus_dout[31:0]),
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.data_out(tmr0_data_out[31:0]),
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.data_out(tmr0_dout[31:0]),
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.wt(tmr0_wt),
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.ack(tmr0_ack),
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.irq(tmr0_irq)
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.irq(tmr0_irq)
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);
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);
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tmr tmr1_1(
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tmr tmr_2(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.rst(rst),
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.en(tmr1_en),
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.stb(tmr1_stb),
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.wr(tmr1_wr),
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.we(bus_we),
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.addr(tmr1_addr[3:2]),
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.addr(bus_addr[3:2]),
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.data_in(tmr1_data_in[31:0]),
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.data_in(bus_dout[31:0]),
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.data_out(tmr1_data_out[31:0]),
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.data_out(tmr1_dout[31:0]),
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.wt(tmr1_wt),
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.ack(tmr1_ack),
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.irq(tmr1_irq)
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.irq(tmr1_irq)
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);
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);
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|
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dsp dsp1(
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dsp dsp_1(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.rst(rst),
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.en(dsp_en),
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.stb(dsp_stb),
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.wr(dsp_wr),
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.we(bus_we),
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.addr(dsp_addr[13:2]),
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.addr(bus_addr[13:2]),
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.data_in(dsp_data_in[15:0]),
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.data_in(bus_dout[15:0]),
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.data_out(dsp_data_out[15:0]),
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.data_out(dsp_dout[15:0]),
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.wt(dsp_wt),
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.ack(dsp_ack),
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.hsync(vga_hsync),
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.hsync(vga_hsync),
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.vsync(vga_vsync),
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.vsync(vga_vsync),
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.r(vga_r[2:0]),
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.r(vga_r[2:0]),
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.g(vga_g[2:0]),
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.g(vga_g[2:0]),
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.b(vga_b[2:0])
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.b(vga_b[2:0])
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);
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);
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|
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kbd kbd1(
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kbd kbd_1(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.rst(rst),
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.en(kbd_en),
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.stb(kbd_stb),
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.wr(kbd_wr),
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.we(bus_we),
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.addr(kbd_addr),
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.addr(bus_addr[2]),
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.data_in(kbd_data_in[7:0]),
|
.data_in(bus_dout[7:0]),
|
.data_out(kbd_data_out[7:0]),
|
.data_out(kbd_dout[7:0]),
|
.wt(kbd_wt),
|
.ack(kbd_ack),
|
.irq(kbd_irq),
|
.irq(kbd_irq),
|
.ps2_clk(ps2_clk),
|
.ps2_clk(ps2_clk),
|
.ps2_data(ps2_data)
|
.ps2_data(ps2_data)
|
);
|
);
|
|
|
ser ser1_0(
|
ser ser_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.rst(rst),
|
.en(ser0_en),
|
.stb(ser0_stb),
|
.wr(ser0_wr),
|
.we(bus_we),
|
.addr(ser0_addr[3:2]),
|
.addr(bus_addr[3:2]),
|
.data_in(ser0_data_in[7:0]),
|
.data_in(bus_dout[7:0]),
|
.data_out(ser0_data_out[7:0]),
|
.data_out(ser0_dout[7:0]),
|
.wt(ser0_wt),
|
.ack(ser0_ack),
|
.irq_r(ser0_irq_r),
|
.irq_r(ser0_irq_r),
|
.irq_t(ser0_irq_t),
|
.irq_t(ser0_irq_t),
|
.rxd(rs232_0_rxd),
|
.rxd(rs232_0_rxd),
|
.txd(rs232_0_txd)
|
.txd(rs232_0_txd)
|
);
|
);
|
|
|
ser ser1_1(
|
ser ser_2(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.rst(rst),
|
.en(ser1_en),
|
.stb(ser1_stb),
|
.wr(ser1_wr),
|
.we(bus_we),
|
.addr(ser1_addr[3:2]),
|
.addr(bus_addr[3:2]),
|
.data_in(ser1_data_in[7:0]),
|
.data_in(bus_dout[7:0]),
|
.data_out(ser1_data_out[7:0]),
|
.data_out(ser1_dout[7:0]),
|
.wt(ser1_wt),
|
.ack(ser1_ack),
|
.irq_r(ser1_irq_r),
|
.irq_r(ser1_irq_r),
|
.irq_t(ser1_irq_t),
|
.irq_t(ser1_irq_t),
|
.rxd(rs232_1_rxd),
|
.rxd(rs232_1_rxd),
|
.txd(rs232_1_txd)
|
.txd(rs232_1_txd)
|
);
|
);
|
|
|
dsk dsk1(
|
assign pbus_a[4:3] = 2'b00;
|
|
|
|
dsk dsk_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.rst(rst),
|
.en(dsk_en),
|
.stb(dsk_stb),
|
.wr(dsk_wr),
|
.we(bus_we),
|
.addr(dsk_addr[19:2]),
|
.addr(bus_addr[19:2]),
|
.data_in(dsk_data_in[31:0]),
|
.data_in(bus_dout[31:0]),
|
.data_out(dsk_data_out[31:0]),
|
.data_out(dsk_dout[31:0]),
|
.wt(dsk_wt),
|
.ack(dsk_ack),
|
.irq(dsk_irq),
|
.irq(dsk_irq),
|
.ata_d(pbus_d[15:0]),
|
.ata_d(pbus_d[15:0]),
|
.ata_a(pbus_a[2:0]),
|
.ata_a(pbus_a[2:0]),
|
.ata_cs0_n(ata_cs0_n),
|
.ata_cs0_n(ata_cs0_n),
|
.ata_cs1_n(ata_cs1_n),
|
.ata_cs1_n(ata_cs1_n),
|
| Line 503... |
Line 371... |
.ata_dmarq(ata_dmarq),
|
.ata_dmarq(ata_dmarq),
|
.ata_dmack_n(ata_dmack_n),
|
.ata_dmack_n(ata_dmack_n),
|
.ata_iordy(ata_iordy)
|
.ata_iordy(ata_iordy)
|
);
|
);
|
|
|
fms fms1(
|
fms fms_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.rst(rst),
|
.en(fms_en),
|
.stb(fms_stb),
|
.wr(fms_wr),
|
.we(bus_we),
|
.addr(fms_addr[11:2]),
|
.addr(bus_addr[11:2]),
|
.data_in(fms_data_in[31:0]),
|
.data_in(bus_dout[31:0]),
|
.data_out(fms_data_out[31:0]),
|
.data_out(fms_dout[31:0]),
|
.wt(fms_wt),
|
.ack(fms_ack),
|
.next(dac_next),
|
.next(dac_next),
|
.sample_l(dac_sample_l[15:0]),
|
.sample_l(dac_sample_l[15:0]),
|
.sample_r(dac_sample_r[15:0])
|
.sample_r(dac_sample_r[15:0])
|
);
|
);
|
|
|
dac dac1(
|
dac dac_1(
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.rst(rst),
|
.sample_l(dac_sample_l[15:0]),
|
.sample_l(dac_sample_l[15:0]),
|
.sample_r(dac_sample_r[15:0]),
|
.sample_r(dac_sample_r[15:0]),
|
.next(dac_next),
|
.next(dac_next),
|
.mclk(dac_mclk),
|
.mclk(dac_mclk),
|
.sclk(dac_sclk),
|
.sclk(dac_sclk),
|
.lrck(dac_lrck),
|
.lrck(dac_lrck),
|
.sdti(dac_sdti)
|
.sdti(dac_sdti)
|
);
|
);
|
|
|
assign pbus_a[4:3] = 2'b00;
|
assign slot1_cs_n = 1'b1;
|
assign slot1_cs_n = 1;
|
assign slot2_cs_n = 1'b1;
|
assign slot2_cs_n = 1;
|
assign ether_cs_n = 1'b1;
|
assign ether_cs_n = 1;
|
|
|
bio bio_1(
|
bio bio1(
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.reset(reset),
|
.stb(bio_stb),
|
.en(bio_en),
|
.we(bus_we),
|
.wr(bio_wr),
|
.addr(bus_addr[2]),
|
.addr(bio_addr),
|
.data_in(bus_dout[31:0]),
|
.data_in(bio_data_in[31:0]),
|
.data_out(bio_dout[31:0]),
|
.data_out(bio_data_out[31:0]),
|
.ack(bio_ack),
|
.wt(bio_wt),
|
|
.sw1_1(flash_a[19]),
|
.sw1_1(flash_a[19]),
|
.sw1_2(flash_a[18]),
|
.sw1_2(flash_a[18]),
|
.sw1_3(sw1_3),
|
.sw1_3(sw1_3),
|
.sw1_4(sw1_4),
|
.sw1_4(sw1_4),
|
.sw2_n(sw2_n),
|
.sw2_n(sw2_n),
|
.sw3_n(sw3_n)
|
.sw3_n(sw3_n)
|
);
|
);
|
|
|
|
//--------------------------------------
|
|
// address decoder
|
|
//--------------------------------------
|
|
|
|
// RAM: architectural limit = 512 MB
|
|
// implementation limit = 32 MB
|
|
assign ram_stb =
|
|
(bus_stb == 1 && bus_addr[31:29] == 3'b000
|
|
&& bus_addr[28:25] == 4'b0000) ? 1 : 0;
|
|
|
|
// ROM: architectural limit = 256 MB
|
|
// implementation limit = 2 MB
|
|
assign rom_stb =
|
|
(bus_stb == 1 && bus_addr[31:28] == 4'b0010
|
|
&& bus_addr[27:21] == 7'b0000000) ? 1 : 0;
|
|
|
|
// I/O: architectural limit = 256 MB
|
|
assign i_o_stb =
|
|
(bus_stb == 1 && bus_addr[31:28] == 4'b0011) ? 1 : 0;
|
|
assign tmr0_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h00
|
|
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
|
|
assign tmr1_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h00
|
|
&& bus_addr[19:12] == 8'h01) ? 1 : 0;
|
|
assign dsp_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h01) ? 1 : 0;
|
|
assign kbd_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h02) ? 1 : 0;
|
|
assign ser0_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h03
|
|
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
|
|
assign ser1_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h03
|
|
&& bus_addr[19:12] == 8'h01) ? 1 : 0;
|
|
assign dsk_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h04) ? 1 : 0;
|
|
assign fms_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h05
|
|
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
|
|
assign bio_stb =
|
|
(i_o_stb == 1 && bus_addr[27:20] == 8'h10
|
|
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
|
|
|
|
//--------------------------------------
|
|
// data and acknowledge multiplexers
|
|
//--------------------------------------
|
|
|
|
assign bus_din[31:0] =
|
|
(ram_stb == 1) ? ram_dout[31:0] :
|
|
(rom_stb == 1) ? rom_dout[31:0] :
|
|
(tmr0_stb == 1) ? tmr0_dout[31:0] :
|
|
(tmr1_stb == 1) ? tmr1_dout[31:0] :
|
|
(dsp_stb == 1) ? { 16'h0000, dsp_dout[15:0] } :
|
|
(kbd_stb == 1) ? { 24'h000000, kbd_dout[7:0] } :
|
|
(ser0_stb == 1) ? { 24'h000000, ser0_dout[7:0] } :
|
|
(ser1_stb == 1) ? { 24'h000000, ser1_dout[7:0] } :
|
|
(dsk_stb == 1) ? dsk_dout[31:0] :
|
|
(fms_stb == 1) ? fms_dout[31:0] :
|
|
(bio_stb == 1) ? bio_dout[31:0] :
|
|
32'h00000000;
|
|
|
|
assign bus_ack =
|
|
(ram_stb == 1) ? ram_ack :
|
|
(rom_stb == 1) ? rom_ack :
|
|
(tmr0_stb == 1) ? tmr0_ack :
|
|
(tmr1_stb == 1) ? tmr1_ack :
|
|
(dsp_stb == 1) ? dsp_ack :
|
|
(kbd_stb == 1) ? kbd_ack :
|
|
(ser0_stb == 1) ? ser0_ack :
|
|
(ser1_stb == 1) ? ser1_ack :
|
|
(dsk_stb == 1) ? dsk_ack :
|
|
(fms_stb == 1) ? fms_ack :
|
|
(bio_stb == 1) ? bio_ack :
|
|
0;
|
|
|
|
//--------------------------------------
|
|
// bus interrupt request assignments
|
|
//--------------------------------------
|
|
|
|
assign bus_irq[15] = tmr1_irq;
|
|
assign bus_irq[14] = tmr0_irq;
|
|
assign bus_irq[13] = 0;
|
|
assign bus_irq[12] = 0;
|
|
assign bus_irq[11] = 0;
|
|
assign bus_irq[10] = 0;
|
|
assign bus_irq[ 9] = 0;
|
|
assign bus_irq[ 8] = dsk_irq;
|
|
assign bus_irq[ 7] = 0;
|
|
assign bus_irq[ 6] = 0;
|
|
assign bus_irq[ 5] = 0;
|
|
assign bus_irq[ 4] = kbd_irq;
|
|
assign bus_irq[ 3] = ser1_irq_r;
|
|
assign bus_irq[ 2] = ser1_irq_t;
|
|
assign bus_irq[ 1] = ser0_irq_r;
|
|
assign bus_irq[ 0] = ser0_irq_t;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
