| Line 2448... |
Line 2448... |
// sregs -- the special registers
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// sregs -- the special registers
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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module sregs(clk, reset,
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module sregs(clk, reset,
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rn, we, di, do,
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rn, we, din, dout,
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psw, psw_we, psw_new,
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psw, psw_we, psw_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
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input clk;
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input clk;
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input reset;
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input reset;
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input [2:0] rn;
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input [2:0] rn;
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input we;
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input we;
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input [31:0] di;
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input [31:0] din;
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output [31:0] do;
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output [31:0] dout;
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output [31:0] psw;
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output [31:0] psw;
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input psw_we;
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input psw_we;
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input [31:0] psw_new;
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input [31:0] psw_new;
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output [31:0] tlb_index;
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output [31:0] tlb_index;
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input tlb_index_we;
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input tlb_index_we;
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| Line 2487... |
Line 2487... |
// 110 - not used -
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// 110 - not used -
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// 111 - not used -
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// 111 - not used -
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reg [31:0] sr[0:7];
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reg [31:0] sr[0:7];
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assign do = sr[rn];
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assign dout = sr[rn];
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assign psw = sr[0];
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assign psw = sr[0];
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assign tlb_index = sr[1];
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assign tlb_index = sr[1];
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assign tlb_entry_hi = sr[2];
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assign tlb_entry_hi = sr[2];
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assign tlb_entry_lo = sr[3];
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assign tlb_entry_lo = sr[3];
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assign mmu_bad_addr = sr[4];
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assign mmu_bad_addr = sr[4];
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| Line 2499... |
Line 2499... |
always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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sr[0] <= 32'h00000000;
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sr[0] <= 32'h00000000;
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end else begin
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end else begin
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if (we == 1) begin
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if (we == 1) begin
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sr[rn] <= di;
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sr[rn] <= din;
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end else begin
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end else begin
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if (psw_we) begin
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if (psw_we) begin
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sr[0] <= psw_new;
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sr[0] <= psw_new;
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end
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end
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if (tlb_index_we) begin
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if (tlb_index_we) begin
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