| Line 97... |
Line 97... |
wire tlb_entry_lo_we; // tlb entry lo write enable
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wire tlb_entry_lo_we; // tlb entry lo write enable
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wire [31:0] tlb_entry_lo_new; // new tlb entry lo contents
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wire [31:0] tlb_entry_lo_new; // new tlb entry lo contents
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wire [31:0] mmu_bad_addr; // special register 4 (mmu bad addr) contents
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wire [31:0] mmu_bad_addr; // special register 4 (mmu bad addr) contents
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wire mmu_bad_addr_we; // mmu bad addr write enable
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wire mmu_bad_addr_we; // mmu bad addr write enable
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wire [31:0] mmu_bad_addr_new; // new mmu bad addr contents
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wire [31:0] mmu_bad_addr_new; // new mmu bad addr contents
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wire [31:0] mmu_bad_accs; // special register 5 (mmu bad accs) contents
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wire mmu_bad_accs_we; // mmu bad accs write enable
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wire [31:0] mmu_bad_accs_new; // new mmu bad accs contents
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// mmu & tlb
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// mmu & tlb
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wire tlb_kmissed; // page not found in tlb, MSB of addr is 1
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wire tlb_kmissed; // page not found in tlb, MSB of addr is 1
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wire tlb_umissed; // page not found in tlb, MSB of addr is 0
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wire tlb_umissed; // page not found in tlb, MSB of addr is 0
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wire tlb_invalid; // tlb entry is invalid
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wire tlb_invalid; // tlb entry is invalid
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| Line 179... |
Line 182... |
sreg_num, sreg_we, sreg_di, sreg_do,
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sreg_num, sreg_we, sreg_di, sreg_do,
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psw, psw_we, psw_new,
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psw, psw_we, psw_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new,
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mmu_bad_accs, mmu_bad_accs_we, mmu_bad_accs_new);
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assign mmu_bad_addr_new = virt_addr;
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assign mmu_bad_addr_new = virt_addr;
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assign mmu_bad_accs_we = mmu_bad_addr_we;
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assign mmu_bad_accs_new = { 29'b0, bus_wr, bus_size[1:0] };
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// ctrl
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// ctrl
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ctrl ctrl1(clk, reset,
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ctrl ctrl1(clk, reset,
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opcode, alu_equ, alu_ult, alu_slt,
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opcode, alu_equ, alu_ult, alu_slt,
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bus_wt, bus_en, bus_wr, bus_size,
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bus_wt, bus_en, bus_wr, bus_size,
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| Line 903... |
Line 909... |
mar_we = 1'b0;
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mar_we = 1'b0;
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ma_src = 1'b0;
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ma_src = 1'b0;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mdor_we = 1'b0;
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mdor_we = 1'b0;
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bus_en = 1'b0;
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bus_en = 1'b0;
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bus_wr = 1'bx;
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bus_wr = 1'b0; // get bad_accs right in case of exc
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bus_size = 2'b10; // enable illegal address detection
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bus_size = 2'b10; // enable illegal address detection
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mdir_we = 1'b0;
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mdir_we = 1'b0;
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mdir_sx = 1'bx;
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mdir_sx = 1'bx;
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ir_we = 1'b0;
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ir_we = 1'b0;
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reg_src2 = 2'bxx;
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reg_src2 = 2'bxx;
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| Line 1248... |
Line 1254... |
mar_we = 1'b0;
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mar_we = 1'b0;
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ma_src = 1'b1;
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ma_src = 1'b1;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mdor_we = 1'b0;
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mdor_we = 1'b0;
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bus_en = 1'b0;
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bus_en = 1'b0;
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bus_wr = 1'bx;
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bus_wr = 1'b0; // get bad_accs right in case of exc
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bus_size = ldst_size; // enable illegal address detection
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bus_size = ldst_size; // enable illegal address detection
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mdir_we = 1'b0;
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mdir_we = 1'b0;
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mdir_sx = 1'bx;
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mdir_sx = 1'bx;
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ir_we = 1'b0;
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ir_we = 1'b0;
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reg_src2 = 2'bxx;
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reg_src2 = 2'bxx;
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| Line 1310... |
Line 1316... |
mar_we = 1'b0;
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mar_we = 1'b0;
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ma_src = 1'b1;
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ma_src = 1'b1;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
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mdor_we = 1'b0;
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mdor_we = 1'b0;
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bus_en = 1'b0;
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bus_en = 1'b0;
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bus_wr = 1'bx;
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bus_wr = 1'b1; // get bad_accs right in case of exc
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bus_size = ldst_size; // enable illegal address detection
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bus_size = ldst_size; // enable illegal address detection
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mdir_we = 1'b0;
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mdir_we = 1'b0;
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mdir_sx = 1'bx;
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mdir_sx = 1'bx;
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ir_we = 1'b0;
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ir_we = 1'b0;
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reg_src2 = 2'bxx;
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reg_src2 = 2'bxx;
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| Line 2453... |
Line 2459... |
rn, we, din, dout,
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rn, we, din, dout,
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psw, psw_we, psw_new,
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psw, psw_we, psw_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_index, tlb_index_we, tlb_index_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
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mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new,
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mmu_bad_accs, mmu_bad_accs_we, mmu_bad_accs_new);
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input clk;
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input clk;
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input reset;
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input reset;
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input [2:0] rn;
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input [2:0] rn;
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input we;
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input we;
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input [31:0] din;
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input [31:0] din;
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| Line 2475... |
Line 2482... |
input tlb_entry_lo_we;
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input tlb_entry_lo_we;
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input [31:0] tlb_entry_lo_new;
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input [31:0] tlb_entry_lo_new;
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output [31:0] mmu_bad_addr;
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output [31:0] mmu_bad_addr;
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input mmu_bad_addr_we;
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input mmu_bad_addr_we;
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input [31:0] mmu_bad_addr_new;
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input [31:0] mmu_bad_addr_new;
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output [31:0] mmu_bad_accs;
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input mmu_bad_accs_we;
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input [31:0] mmu_bad_accs_new;
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// rn = 000 register = PSW
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// rn = 000 register = PSW
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// 001 TLB index
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// 001 TLB index
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// 010 TLB entry high
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// 010 TLB entry high
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// 011 TLB entry low
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// 011 TLB entry low
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// 100 MMU bad address
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// 100 MMU bad address
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// 101 - not used -
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// 101 MMU bad access
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// 110 - not used -
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// 110 - not used -
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// 111 - not used -
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// 111 - not used -
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|
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reg [31:0] sr[0:7];
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reg [31:0] sr[0:7];
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| Line 2493... |
Line 2503... |
assign psw = sr[0];
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assign psw = sr[0];
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assign tlb_index = sr[1];
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assign tlb_index = sr[1];
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assign tlb_entry_hi = sr[2];
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assign tlb_entry_hi = sr[2];
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assign tlb_entry_lo = sr[3];
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assign tlb_entry_lo = sr[3];
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assign mmu_bad_addr = sr[4];
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assign mmu_bad_addr = sr[4];
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assign mmu_bad_accs = sr[5];
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|
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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sr[0] <= 32'h00000000;
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sr[0] <= 32'h00000000;
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end else begin
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end else begin
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| Line 2516... |
Line 2527... |
sr[3] <= tlb_entry_lo_new;
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sr[3] <= tlb_entry_lo_new;
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end
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end
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if (mmu_bad_addr_we) begin
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if (mmu_bad_addr_we) begin
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sr[4] <= mmu_bad_addr_new;
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sr[4] <= mmu_bad_addr_new;
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end
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end
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if (mmu_bad_accs_we) begin
|
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sr[5] <= mmu_bad_accs_new;
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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