OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsk/] [atactrl.v] - Diff between revs 288 and 290

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 288 Rev 290
Line 1... Line 1...
//
//
// atactrl.v -- parallel ATA controller
// atactrl.v -- parallel ATA controller
//
//
 
 
 
 
 
`timescale 1ns/10ps
 
`default_nettype none
 
 
 
 
`define ADDR_ALTERNATE_STATUS   4'b0110
`define ADDR_ALTERNATE_STATUS   4'b0110
`define ADDR_DEVICE_CONTROL     4'b0110
`define ADDR_DEVICE_CONTROL     4'b0110
`define ADDR_DEVICE_ADDRESS     4'b0111
`define ADDR_DEVICE_ADDRESS     4'b0111
`define ADDR_DATA               4'b1000
`define ADDR_DATA               4'b1000
`define ADDR_ERROR              4'b1001
`define ADDR_ERROR              4'b1001
Line 55... Line 59...
wire [15:0] buffer_ata_dout;
wire [15:0] buffer_ata_dout;
wire buffer_bus_addressed;
wire buffer_bus_addressed;
wire buffer_bus_write;
wire buffer_bus_write;
reg buffer_bus_second_cycle;
reg buffer_bus_second_cycle;
 
 
ata_buffer buffer1 (
ata_buffer ata_buffer_1(
    .clk (clk),
    .clk (clk),
    .bus_write (buffer_bus_write),
    .bus_write (buffer_bus_write),
    .bus_addr (bus_addr [11:2]),
    .bus_addr (bus_addr [11:2]),
    .bus_din (bus_din),
    .bus_din (bus_din),
    .bus_dout (buffer_bus_dout),
    .bus_dout (buffer_bus_dout),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.