OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsk/] [dsk.v] - Diff between revs 288 and 290

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 288 Rev 290
Line 1... Line 1... 
//
 
//
 
// dsk.v -- parallel ATA (IDE) disk interface
 
// dsk.v -- parallel ATA (IDE) disk interface
 
//
 
//
 
 
 
 
 
 
 
 
 
module dsk(clk, reset,
 
`timescale 1ns/10ps
 
           en, wr, addr,
 
`default_nettype none
 
 
 
 
 
 
 
 
 
 
 
module dsk(clk, rst,
 
 
 
           stb, we, addr,
 
           data_in, data_out,
 
           data_in, data_out,
 
           wt, irq,
 
           ack, irq,
 
           ata_d, ata_a, ata_cs0_n, ata_cs1_n,
 
           ata_d, ata_a, ata_cs0_n, ata_cs1_n,
 
           ata_dior_n, ata_diow_n, ata_intrq,
 
           ata_dior_n, ata_diow_n, ata_intrq,
 
           ata_dmarq, ata_dmack_n, ata_iordy);
 
           ata_dmarq, ata_dmack_n, ata_iordy);
 
    // internal interface signals
 
    // internal interface signals
 
    input clk;
 
    input clk;
 
    input reset;
 
    input rst;
 
    input en;
 
    input stb;
 
    input wr;
 
    input we;
 
    input [19:2] addr;
 
    input [19:2] addr;
 
    input [31:0] data_in;
 
    input [31:0] data_in;
 
    output [31:0] data_out;
 
    output [31:0] data_out;
 
    output wt;
 
    output ack;
 
    output irq;
 
    output irq;
 
    // external interface signals
 
    // external interface signals
 
    inout [15:0] ata_d;
 
    inout [15:0] ata_d;
 
    output [2:0] ata_a;
 
    output [2:0] ata_a;
 
    output ata_cs0_n, ata_cs1_n;
 
    output ata_cs0_n, ata_cs1_n;
Line 28... Line 32... 
    input ata_intrq;
 
    input ata_intrq;
 
    input ata_dmarq;
 
    input ata_dmarq;
 
    output ata_dmack_n;
 
    output ata_dmack_n;
 
    input ata_iordy;
 
    input ata_iordy;
 
 
 
 
 
  ata_ctrl ata_ctrl1 (
 
  wire bus_wait;
 
 
 
 
 
 
 
  ata_ctrl ata_ctrl_1(
 
    .clk(clk),
 
    .clk(clk),
 
    .reset(reset),
 
    .reset(rst),
 
    .bus_en(en),
 
    .bus_en(stb),
 
    .bus_wr(wr),
 
    .bus_wr(we),
 
    .bus_addr(addr),
 
    .bus_addr(addr),
 
    .bus_din(data_in),
 
    .bus_din(data_in),
 
    .bus_dout(data_out),
 
    .bus_dout(data_out),
 
    .bus_wait(wt),
 
    .bus_wait(bus_wait),
 
    .bus_irq(irq),
 
    .bus_irq(irq),
 
    .ata_d(ata_d),
 
    .ata_d(ata_d),
 
    .ata_a(ata_a),
 
    .ata_a(ata_a),
 
    .ata_cs0_n(ata_cs0_n),
 
    .ata_cs0_n(ata_cs0_n),
 
    .ata_cs1_n(ata_cs1_n),
 
    .ata_cs1_n(ata_cs1_n),
Line 50... Line 56... 
    .ata_dmarq(ata_dmarq),
 
    .ata_dmarq(ata_dmarq),
 
    .ata_dmack_n(ata_dmack_n),
 
    .ata_dmack_n(ata_dmack_n),
 
    .ata_iordy(ata_iordy)
 
    .ata_iordy(ata_iordy)
 
  );
 
  );
 
 
 
 
 
 
 
  assign ack = stb & ~bus_wait;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.