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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsp/] [bpp9/] [dsp.v] - Diff between revs 288 and 290

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Rev 288	Rev 290
Line 1...	Line 1...
`//`	`//`
`// dsp.v -- character display interface`	`// dsp.v -- character display interface`
`//`	`//`


`module dsp(clk, reset,`	`timescale 1ns/10ps
`addr, en, wr, wt,`	`default_nettype none


	`module dsp(clk, rst,`
	`stb, we, addr,`
`data_in, data_out,`	`data_in, data_out,`
	`ack,`
`hsync, vsync,`	`hsync, vsync,`
`r, g, b);`	`r, g, b);`
`// internal interface`	`// internal interface`
`input clk;`	`input clk;`
`input reset;`	`input rst;`
	`input stb;`
	`input we;`
`input [13:2] addr;`	`input [13:2] addr;`
`input en;`
`input wr;`
`output wt;`
`input [15:0] data_in;`	`input [15:0] data_in;`
`output [15:0] data_out;`	`output [15:0] data_out;`
	`output ack;`
`// external interface`	`// external interface`
`output hsync;`	`output hsync;`
`output vsync;`	`output vsync;`
`output [2:0] r;`	`output [2:0] r;`
`output [2:0] g;`	`output [2:0] g;`
`output [2:0] b;`	`output [2:0] b;`

`reg state;`	`reg state;`

`display display1(`	`display display_1(`
`.clk(clk),`	`.clk(clk),`
`.dsp_row(addr[13:9]),`	`.dsp_row(addr[13:9]),`
`.dsp_col(addr[8:2]),`	`.dsp_col(addr[8:2]),`
`.dsp_en(en),`	`.dsp_en(stb),`
`.dsp_wr(wr),`	`.dsp_wr(we),`
`.dsp_wr_data(data_in[15:0]),`	`.dsp_wr_data(data_in[15:0]),`
`.dsp_rd_data(data_out[15:0]),`	`.dsp_rd_data(data_out[15:0]),`
`.hsync(hsync),`	`.hsync(hsync),`
`.vsync(vsync),`	`.vsync(vsync),`
`.r(r[2:0]),`	`.r(r[2:0]),`
`.g(g[2:0]),`	`.g(g[2:0]),`
`.b(b[2:0])`	`.b(b[2:0])`
`);`	`);`

`always @(posedge clk) begin`	`always @(posedge clk) begin`
`if (reset == 1) begin`	`if (rst) begin`
`state <= 1'b0;`	`state <= 1'b0;`
`end else begin`	`end else begin`
`case (state)`	`case (state)`
`1'b0:`	`1'b0:`
`begin`	`begin`
`if (en == 1 && wr == 0) begin`	`if (stb & ~we) begin`
`state <= 1'b1;`	`state <= 1'b1;`
`end`	`end`
`end`	`end`
`1'b1:`	`1'b1:`
`begin`	`begin`
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`end`	`end`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`assign wt = (en == 1 && wr == 0 && state == 1'b0) ? 1 : 0;`	`assign ack = stb & (we \| state);`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsp/] [bpp9/] [dsp.v] - Diff between revs 288 and 290