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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [dsp/] [bpp9/] [pixel.v] - Diff between revs 288 and 290

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//
//
// pixel.v -- last stage in display pipeline
// pixel.v -- last stage in display pipeline
//
//
 
 
 
 
 
`timescale 1ns/10ps
 
`default_nettype none
 
 
 
 
module pixel(clk, pixclk, attcode,
module pixel(clk, pixclk, attcode,
             pixel, blank, hsync_in, vsync_in, blink,
             pixel, blank, hsync_in, vsync_in, blink,
             hsync, vsync, r, g, b);
             hsync, vsync, r, g, b);
    input clk;
    input clk;
    input pixclk;
    input pixclk;

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