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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [fms/] [fms.v] - Diff between revs 288 and 290

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Rev 288 Rev 290
Line 4... Line 4... 
// NOTE: This is a fake module for now.
 
// NOTE: This is a fake module for now.
 
//       It allows writing directly to the DAC.
 
//       It allows writing directly to the DAC.
 
//
 
//
 
 
 
 
 
 
 
 
 
module fms(clk, reset,
 
`timescale 1ns/10ps
 
           en, wr, addr,
 
`default_nettype none
 
 
 
 
 
 
 
 
 
 
 
module fms(clk, rst,
 
 
 
           stb, we, addr,
 
           data_in, data_out,
 
           data_in, data_out,
 
           wt,
 
           ack,
 
           next, sample_l, sample_r);
 
           next, sample_l, sample_r);
 
    // internal interface
 
    // internal interface
 
    input clk;
 
    input clk;
 
    input reset;
 
    input rst;
 
    input en;
 
    input stb;
 
    input wr;
 
    input we;
 
    input [11:2] addr;
 
    input [11:2] addr;
 
    input [31:0] data_in;
 
    input [31:0] data_in;
 
    output [31:0] data_out;
 
    output [31:0] data_out;
 
    output wt;
 
    output ack;
 
    // DAC controller interface
 
    // DAC controller interface
 
    input next;
 
    input next;
 
    output [15:0] sample_l;
 
    output [15:0] sample_l;
 
    output [15:0] sample_r;
 
    output [15:0] sample_r;
 
 
 
 
 
  reg [31:0] value;
 
  reg [31:0] value;
 
  reg value_needed;
 
  reg value_needed;
 
 
 
 
 
  always @(posedge clk) begin
 
  always @(posedge clk) begin
 
    if (reset) begin
 
    if (rst) begin
 
      value[31:0] <= 32'h0;
 
      value[31:0] <= 32'h0;
 
      value_needed <= 0;
 
      value_needed <= 0;
 
    end else begin
 
    end else begin
 
      if (en & wr & ~|addr[11:2]) begin
 
      if (stb & we & ~|addr[11:2]) begin
 
        value[31:0] <= data_in[31:0];
 
        value[31:0] <= data_in[31:0];
 
        value_needed <= 0;
 
        value_needed <= 0;
 
      end else begin
 
      end else begin
 
        if (next) begin
 
        if (next) begin
 
          value_needed <= 1;
 
          value_needed <= 1;
Line 43... Line 47... 
      end
 
      end
 
    end
 
    end
 
  end
 
  end
 
 
 
 
 
  assign data_out[31:0] = { 31'h0, value_needed };
 
  assign data_out[31:0] = { 31'h0, value_needed };
 
  assign wt = 0;
 
  assign ack = stb;
 
 
 
 
 
  assign sample_l[15:0] = value[31:16];
 
  assign sample_l[15:0] = value[31:16];
 
  assign sample_r[15:0] = value[15:0];
 
  assign sample_r[15:0] = value[15:0];
 
 
 
 
 
endmodule
 
endmodule

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