URL
https://opencores.org/ocsvn/eco32/eco32/trunk
[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [kbd/] [kbd.v] - Diff between revs 67 and 116
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 67 |
Rev 116 |
| Line 1... |
Line 1... |
module kbd(ps2_clk, ps2_data,
|
//
|
clk, reset,
|
// kbd.v -- PC keyboard interface
|
|
//
|
|
|
|
|
|
module kbd(clk, reset,
|
en, wr, addr,
|
en, wr, addr,
|
data_in, data_out,
|
data_in, data_out,
|
wt, irq);
|
wt, irq,
|
input ps2_clk;
|
ps2_clk, ps2_data);
|
input ps2_data;
|
// internal interface
|
input clk;
|
input clk;
|
input reset;
|
input reset;
|
input en;
|
input en;
|
input wr;
|
input wr;
|
input addr;
|
input addr;
|
input [7:0] data_in;
|
input [7:0] data_in;
|
output [7:0] data_out;
|
output [7:0] data_out;
|
output wt;
|
output wt;
|
output irq;
|
output irq;
|
|
// external interface
|
|
input ps2_clk;
|
|
input ps2_data;
|
|
|
wire [7:0] keyboard_data;
|
wire [7:0] keyboard_data;
|
wire keyboard_rdy;
|
wire keyboard_rdy;
|
reg [7:0] data;
|
reg [7:0] data;
|
reg rdy;
|
reg rdy;
|
reg ien;
|
reg ien;
|
|
reg [7:2] other_bits;
|
|
|
keyboard keyboard1(
|
keyboard keyboard1(
|
.ps2_clk(ps2_clk),
|
.ps2_clk(ps2_clk),
|
.ps2_data(ps2_data),
|
.ps2_data(ps2_data),
|
.clk(clk),
|
.clk(clk),
|
| Line 33... |
Line 41... |
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if (reset == 1) begin
|
if (reset == 1) begin
|
data <= 8'h00;
|
data <= 8'h00;
|
rdy <= 0;
|
rdy <= 0;
|
ien <= 0;
|
ien <= 0;
|
|
other_bits <= 6'b000000;
|
end else begin
|
end else begin
|
if (keyboard_rdy == 1) begin
|
if (keyboard_rdy == 1) begin
|
data <= keyboard_data;
|
data <= keyboard_data;
|
end
|
end
|
if (keyboard_rdy == 1 ||
|
if (keyboard_rdy == 1 ||
|
| Line 44... |
Line 53... |
rdy <= keyboard_rdy;
|
rdy <= keyboard_rdy;
|
end
|
end
|
if (en == 1 && wr == 1 && addr == 0) begin
|
if (en == 1 && wr == 1 && addr == 0) begin
|
rdy <= data_in[0];
|
rdy <= data_in[0];
|
ien <= data_in[1];
|
ien <= data_in[1];
|
|
other_bits <= data_in[7:2];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
assign data_out =
|
assign data_out =
|
(addr == 0) ? { 6'b000000, ien, rdy } : data;
|
(addr == 0) ? { other_bits[7:2], ien, rdy } : data[7:0];
|
assign wt = 1'b0;
|
assign wt = 1'b0;
|
assign irq = ien & rdy;
|
assign irq = ien & rdy;
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.