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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [kbd/] [kbd.v] - Diff between revs 288 and 290

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//
//
// kbd.v -- PC keyboard interface
// kbd.v -- PS/2 keyboard interface
//
//
 
 
 
 
module kbd(clk, reset,
`timescale 1ns/10ps
           en, wr, addr,
`default_nettype none
 
 
 
 
 
module kbd(clk, rst,
 
           stb, we, addr,
           data_in, data_out,
           data_in, data_out,
           wt, irq,
           ack, irq,
           ps2_clk, ps2_data);
           ps2_clk, ps2_data);
    // internal interface
    // internal interface
    input clk;
    input clk;
    input reset;
    input rst;
    input en;
    input stb;
    input wr;
    input we;
    input addr;
    input addr;
    input [7:0] data_in;
    input [7:0] data_in;
    output [7:0] data_out;
    output [7:0] data_out;
    output wt;
    output ack;
    output irq;
    output irq;
    // external interface
    // external interface
    input ps2_clk;
    input ps2_clk;
    input ps2_data;
    input ps2_data;
 
 
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  reg [7:0] data;
  reg [7:0] data;
  reg rdy;
  reg rdy;
  reg ien;
  reg ien;
  reg [7:2] other_bits;
  reg [7:2] other_bits;
 
 
  keyboard keyboard1(
  keyboard keyboard_1(
    .ps2_clk(ps2_clk),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .ps2_data(ps2_data),
    .clk(clk),
    .clk(clk),
    .reset(reset),
    .rst(rst),
    .keyboard_data(keyboard_data[7:0]),
    .keyboard_data(keyboard_data[7:0]),
    .keyboard_rdy(keyboard_rdy)
    .keyboard_rdy(keyboard_rdy)
  );
  );
 
 
  always @(posedge clk) begin
  always @(posedge clk) begin
    if (reset == 1) begin
    if (rst) begin
      data <= 8'h00;
      data <= 8'h00;
      rdy <= 0;
      rdy <= 0;
      ien <= 0;
      ien <= 0;
      other_bits <= 6'b000000;
      other_bits <= 6'b000000;
    end else begin
    end else begin
      if (keyboard_rdy == 1) begin
      if (keyboard_rdy == 1) begin
        data <= keyboard_data;
        data <= keyboard_data;
      end
      end
      if (keyboard_rdy == 1 ||
      if (keyboard_rdy == 1 ||
          (en == 1 && wr == 0 && addr == 1)) begin
          (stb == 1 && we == 0 && addr == 1)) begin
        rdy <= keyboard_rdy;
        rdy <= keyboard_rdy;
      end
      end
      if (en == 1 && wr == 1 && addr == 0) begin
      if (stb == 1 && we == 1 && addr == 0) begin
        rdy <= data_in[0];
        rdy <= data_in[0];
        ien <= data_in[1];
        ien <= data_in[1];
        other_bits <= data_in[7:2];
        other_bits <= data_in[7:2];
      end
      end
    end
    end
  end
  end
 
 
  assign data_out =
  assign data_out =
    (addr == 0) ? { other_bits[7:2], ien, rdy } : data[7:0];
    (addr == 0) ? { other_bits[7:2], ien, rdy } : data[7:0];
  assign wt = 1'b0;
  assign ack = stb;
  assign irq = ien & rdy;
  assign irq = ien & rdy;
 
 
endmodule
endmodule
 
 
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