Subversion Repositories eco32

//

//

// keyboard.v -- PC keyboard receiver

// keyboard.v -- PC keyboard receiver

//

//

module keyboard(ps2_clk, ps2_data,

module keyboard(ps2_clk, ps2_data,

                keyboard_data, keyboard_rdy);

                keyboard_data, keyboard_rdy);

    input ps2_clk;

    input ps2_clk;

    input ps2_data;

    input ps2_data;

    input clk;

    input clk;

    output [7:0] keyboard_data;

    output [7:0] keyboard_data;

    output keyboard_rdy;

    output keyboard_rdy;

  reg ps2_clk_p;

  reg ps2_clk_p;

  reg ps2_clk_s;

  reg ps2_clk_s;

    (ps2_clk_s == 1) ? ps2_clk_int_r + 1 :

    (ps2_clk_s == 1) ? ps2_clk_int_r + 1 :

    ps2_clk_int_r - 1;

    ps2_clk_int_r - 1;

  // clock level detector with hysteresis

  // clock level detector with hysteresis

  always @(posedge clk) begin

  always @(posedge clk) begin

      ps2_clk_lvl_prv <= 1;

      ps2_clk_lvl_prv <= 1;

      ps2_clk_lvl <= 1;

      ps2_clk_lvl <= 1;

    end else begin

    end else begin

      ps2_clk_lvl_prv <= ps2_clk_lvl;

      ps2_clk_lvl_prv <= ps2_clk_lvl;

      if (ps2_clk_int_r == 4'b0100) begin

      if (ps2_clk_int_r == 4'b0100) begin

      bitcnt_r != 4'b1011 &&

      bitcnt_r != 4'b1011 &&

      bitcnt_r != 4'b0000)) ? 1 : err_r;

      bitcnt_r != 4'b0000)) ? 1 : err_r;

  // update state registers

  // update state registers

  always @(posedge clk) begin

  always @(posedge clk) begin

      ps2_clk_int_r <= 4'b1111;

      ps2_clk_int_r <= 4'b1111;

      data_r <= 10'b0000000000;

      data_r <= 10'b0000000000;

      timer_r <= 13'b0000000000000;

      timer_r <= 13'b0000000000000;

      bitcnt_r <= 4'b0000;

      bitcnt_r <= 4'b0000;

      rdy_r <= 0;

      rdy_r <= 0;