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Line 1... |
//
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//
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// ram_2.v -- main memory, using DDR SDRAM
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// ram.v -- external RAM interface, using DDR SDRAM
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// 16M x 32 bit = 64 MB
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//
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//
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`timescale 1ns/10ps
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`default_nettype none
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module ram(ddr_clk_0, ddr_clk_90, ddr_clk_180,
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module ram(ddr_clk_0, ddr_clk_90, ddr_clk_180,
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ddr_clk_270, ddr_clk_ok, clk, reset,
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ddr_clk_270, ddr_clk_ok, clk, rst,
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en, wr, size, addr,
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stb, we, addr, data_in, data_out, ack,
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data_in, data_out, wt,
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sdram_ck_p, sdram_ck_n, sdram_cke,
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sdram_ck_p, sdram_ck_n, sdram_cke,
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sdram_cs_n, sdram_ras_n, sdram_cas_n,
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sdram_cs_n, sdram_ras_n, sdram_cas_n,
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sdram_we_n, sdram_ba, sdram_a,
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sdram_we_n, sdram_ba, sdram_a,
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sdram_udm, sdram_ldm,
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sdram_udm, sdram_ldm,
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sdram_udqs, sdram_ldqs, sdram_dq);
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sdram_udqs, sdram_ldqs, sdram_dq);
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| Line 17... |
Line 21... |
input ddr_clk_90;
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input ddr_clk_90;
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input ddr_clk_180;
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input ddr_clk_180;
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input ddr_clk_270;
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input ddr_clk_270;
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input ddr_clk_ok;
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input ddr_clk_ok;
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input clk;
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input clk;
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input reset;
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input rst;
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input en;
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input stb;
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input wr;
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input we;
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input [1:0] size;
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input [25:2] addr;
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input [25:0] addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output reg [31:0] data_out;
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output [31:0] data_out;
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output wt;
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output ack;
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// DDR SDRAM interface signals
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// DDR SDRAM interface signals
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output sdram_ck_p;
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output sdram_ck_p;
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output sdram_ck_n;
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output sdram_ck_n;
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output sdram_cke;
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output sdram_cke;
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output sdram_cs_n;
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output sdram_cs_n;
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Line 44... |
output sdram_ldm;
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output sdram_ldm;
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inout sdram_udqs;
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inout sdram_udqs;
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inout sdram_ldqs;
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inout sdram_ldqs;
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inout [15:0] sdram_dq;
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inout [15:0] sdram_dq;
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wire [31:0] do;
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ddr_sdram ddr_sdram_1(
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reg [31:0] di;
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reg [3:0] wb;
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wire ack;
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ddr_sdram ddr_sdram1(
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.sd_CK_P(sdram_ck_p),
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.sd_CK_P(sdram_ck_p),
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.sd_CK_N(sdram_ck_n),
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.sd_CK_N(sdram_ck_n),
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.sd_A_O(sdram_a[12:0]),
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.sd_A_O(sdram_a[12:0]),
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.sd_BA_O(sdram_ba[1:0]),
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.sd_BA_O(sdram_ba[1:0]),
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.sd_D_IO(sdram_dq[15:0]),
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.sd_D_IO(sdram_dq[15:0]),
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| Line 67... |
Line 65... |
.clk90(ddr_clk_90),
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.clk90(ddr_clk_90),
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.clk180(ddr_clk_180),
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.clk180(ddr_clk_180),
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.clk270(ddr_clk_270),
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.clk270(ddr_clk_270),
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.reset(~ddr_clk_ok),
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.reset(~ddr_clk_ok),
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.wADR_I(addr[25:2]),
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.wADR_I(addr[25:2]),
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.wSTB_I(en),
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.wSTB_I(stb),
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.wWE_I(wr),
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.wWE_I(we),
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.wWRB_I(wb[3:0]),
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.wWRB_I(4'b1111),
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.wDAT_I(di[31:0]),
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.wDAT_I(data_in[31:0]),
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.wDAT_O(do[31:0]),
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.wDAT_O(data_out[31:0]),
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.wACK_O(ack)
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.wACK_O(ack)
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);
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);
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// read multiplexer
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always @(*) begin
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case (size[1:0])
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2'b00:
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// byte
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begin
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data_out[31:24] = 8'hxx;
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data_out[23:16] = 8'hxx;
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data_out[15: 8] = 8'hxx;
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if (addr[1] == 0) begin
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if (addr[0] == 0) begin
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data_out[ 7: 0] = do[31:24];
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end else begin
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data_out[ 7: 0] = do[23:16];
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end
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end else begin
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if (addr[0] == 0) begin
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data_out[ 7: 0] = do[15: 8];
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end else begin
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data_out[ 7: 0] = do[ 7: 0];
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end
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end
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end
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2'b01:
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// halfword
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begin
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data_out[31:24] = 8'hxx;
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data_out[23:16] = 8'hxx;
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if (addr[1] == 0) begin
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data_out[15: 8] = do[31:24];
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data_out[ 7: 0] = do[23:16];
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end else begin
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data_out[15: 8] = do[15: 8];
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data_out[ 7: 0] = do[ 7: 0];
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end
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end
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2'b10:
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// word
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begin
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data_out[31:24] = do[31:24];
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data_out[23:16] = do[23:16];
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data_out[15: 8] = do[15: 8];
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data_out[ 7: 0] = do[ 7: 0];
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end
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default:
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// illegal
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begin
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data_out[31:24] = 8'hxx;
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data_out[23:16] = 8'hxx;
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data_out[15: 8] = 8'hxx;
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data_out[ 7: 0] = 8'hxx;
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end
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endcase
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end
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// write multiplexer & data masks
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always @(*) begin
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case (size[1:0])
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2'b00:
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// byte
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begin
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di[31:24] = data_in[ 7: 0];
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di[23:16] = data_in[ 7: 0];
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di[15: 8] = data_in[ 7: 0];
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di[ 7: 0] = data_in[ 7: 0];
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wb[3] = ~addr[1] & ~addr[0];
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wb[2] = ~addr[1] & addr[0];
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wb[1] = addr[1] & ~addr[0];
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wb[0] = addr[1] & addr[0];
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end
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2'b01:
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// halfword
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begin
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di[31:24] = data_in[15: 8];
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di[23:16] = data_in[ 7: 0];
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di[15: 8] = data_in[15: 8];
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di[ 7: 0] = data_in[ 7: 0];
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wb[3] = ~addr[1];
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wb[2] = ~addr[1];
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wb[1] = addr[1];
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wb[0] = addr[1];
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end
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2'b10:
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// word
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begin
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di[31:24] = data_in[31:24];
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di[23:16] = data_in[23:16];
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di[15: 8] = data_in[15: 8];
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di[ 7: 0] = data_in[ 7: 0];
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wb[3] = 1'b1;
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wb[2] = 1'b1;
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wb[1] = 1'b1;
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wb[0] = 1'b1;
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end
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default:
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// illegal
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begin
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di[31:24] = 8'hxx;
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di[23:16] = 8'hxx;
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di[15: 8] = 8'hxx;
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di[ 7: 0] = 8'hxx;
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wb[3] = 1'b0;
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wb[2] = 1'b0;
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wb[1] = 1'b0;
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wb[0] = 1'b0;
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end
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endcase
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end
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assign wt = ~ack;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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