URL
https://opencores.org/ocsvn/eco32/eco32/trunk
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| Rev 290 |
Rev 291 |
| Line 44... |
Line 44... |
output sdram_ldm;
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output sdram_ldm;
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inout sdram_udqs;
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inout sdram_udqs;
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inout sdram_ldqs;
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inout sdram_ldqs;
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inout [15:0] sdram_dq;
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inout [15:0] sdram_dq;
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//----------------------------------------------------
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// This is a hack. The synthesizer detected setup timing
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// violations on wDAT_I that resulted from crossing the
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// 50 MHz to 100 MHz clock domain border. The circuit would
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// have functioned perfectly ok, because the signals are
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// used only on the following 100 MHz clock edge, a fact
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// that the synthesizer was unable to deduce. Instead of
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// tolerating formal errors during synthesis, I tried to
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// insert a register that is clocked with the trailing
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// edge of the 50 MHz clock. Surprisingly, this worked.
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reg [31:0] data_in_buf;
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always @(negedge clk) begin
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data_in_buf[31:0] <= data_in[31:0];
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end
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//----------------------------------------------------
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ddr_sdram ddr_sdram_1(
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ddr_sdram ddr_sdram_1(
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.sd_CK_P(sdram_ck_p),
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.sd_CK_P(sdram_ck_p),
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.sd_CK_N(sdram_ck_n),
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.sd_CK_N(sdram_ck_n),
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.sd_A_O(sdram_a[12:0]),
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.sd_A_O(sdram_a[12:0]),
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.sd_BA_O(sdram_ba[1:0]),
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.sd_BA_O(sdram_ba[1:0]),
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| Line 68... |
Line 88... |
.reset(~ddr_clk_ok),
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.reset(~ddr_clk_ok),
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.wADR_I(addr[25:2]),
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.wADR_I(addr[25:2]),
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.wSTB_I(stb),
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.wSTB_I(stb),
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.wWE_I(we),
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.wWE_I(we),
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.wWRB_I(4'b1111),
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.wWRB_I(4'b1111),
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.wDAT_I(data_in[31:0]),
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.wDAT_I(data_in_buf[31:0]),
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.wDAT_O(data_out[31:0]),
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.wDAT_O(data_out[31:0]),
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.wACK_O(ack)
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.wACK_O(ack)
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);
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);
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endmodule
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endmodule
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