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Line 1... |
//
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//
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// ram.v -- main memory, using SDRAM
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// ram.v -- external RAM interface, using SDRAM
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// 8M x 32 bit = 32 MB
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//
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//
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module ram(clk, clk_ok, reset,
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`timescale 1ns/10ps
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en, wr, size, addr,
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`default_nettype none
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data_in, data_out, wt,
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module ram(clk, clk_ok, rst,
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stb, we, addr,
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data_in, data_out, ack,
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sdram_cke, sdram_cs_n,
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sdram_cke, sdram_cs_n,
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sdram_ras_n, sdram_cas_n,
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sdram_ras_n, sdram_cas_n,
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sdram_we_n, sdram_ba, sdram_a,
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sdram_we_n, sdram_ba, sdram_a,
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sdram_udqm, sdram_ldqm, sdram_dq);
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sdram_udqm, sdram_ldqm, sdram_dq);
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// internal interface signals
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// internal interface signals
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input clk;
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input clk;
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input clk_ok;
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input clk_ok;
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input reset;
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input rst;
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input en;
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input stb;
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input wr;
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input we;
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input [1:0] size;
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input [24:2] addr;
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input [24:0] addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output reg [31:0] data_out;
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output reg [31:0] data_out;
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output reg wt;
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output reg ack;
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// SDRAM interface signals
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// SDRAM interface signals
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output sdram_cke;
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output sdram_cke;
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output sdram_cs_n;
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output sdram_cs_n;
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output sdram_ras_n;
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output sdram_ras_n;
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output sdram_cas_n;
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output sdram_cas_n;
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| Line 31... |
Line 35... |
output [12:0] sdram_a;
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output [12:0] sdram_a;
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output sdram_udqm;
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output sdram_udqm;
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output sdram_ldqm;
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output sdram_ldqm;
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inout [15:0] sdram_dq;
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inout [15:0] sdram_dq;
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reg [3:0] state;
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reg [2:0] state;
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reg a0;
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reg a0;
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reg cntl_read;
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reg cntl_read;
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reg cntl_write;
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reg cntl_write;
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wire cntl_done;
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wire cntl_done;
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wire [23:0] cntl_addr;
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wire [23:0] cntl_addr;
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| Line 45... |
Line 49... |
wire sd_out_en;
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wire sd_out_en;
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wire [15:0] sd_out;
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wire [15:0] sd_out;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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sdramCntl sdramCntl1(
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sdramCntl sdramCntl_1(
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// clock
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// clock
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.clk(clk),
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.clk(clk),
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.clk_ok(clk_ok),
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.clk_ok(clk_ok),
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// host side
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// host side
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.rd(cntl_read & ~cntl_done),
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.rd(cntl_read & ~cntl_done),
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| Line 77... |
Line 81... |
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// the SDRAM is organized in 16-bit halfwords
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// the SDRAM is organized in 16-bit halfwords
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// address line 0 is controlled by the state machine
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// address line 0 is controlled by the state machine
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// (this is necessary for word accesses)
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assign cntl_addr[23:1] = addr[24:2];
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assign cntl_addr[23:1] = addr[24:2];
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assign cntl_addr[0] = a0;
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assign cntl_addr[0] = a0;
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// state machine for SDRAM access
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// state machine for SDRAM access
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (rst) begin
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state <= 4'b0000;
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state <= 3'b000;
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wt <= 1;
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ack <= 0;
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end else begin
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end else begin
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case (state)
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case (state)
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4'b0000:
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3'b000:
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// wait for access
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// wait for access
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begin
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begin
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if (en == 1) begin
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if (stb) begin
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// access
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// access
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if (wr == 1) begin
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if (we) begin
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// write
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// write
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if (size[1] == 1) begin
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state <= 3'b001;
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// write word
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state <= 4'b0001;
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end else begin
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if (size[0] == 1) begin
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// write halfword
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state <= 4'b0101;
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end else begin
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// write byte
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state <= 4'b0111;
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end
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end
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end else begin
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end else begin
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// read
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// read
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if (size[1] == 1) begin
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state <= 3'b011;
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// read word
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state <= 4'b0011;
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end else begin
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if (size[0] == 1) begin
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// read halfword
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state <= 4'b0110;
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end else begin
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// read byte
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state <= 4'b1001;
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end
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end
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end
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end
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end
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end
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end
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end
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4'b0001:
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3'b001:
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// write word, upper 16 bits
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// write word, upper 16 bits
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begin
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begin
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if (cntl_done == 1) begin
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if (cntl_done) begin
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state <= 4'b0010;
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state <= 3'b010;
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end
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end
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end
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end
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4'b0010:
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3'b010:
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// write word, lower 16 bits
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// write word, lower 16 bits
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begin
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begin
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if (cntl_done == 1) begin
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if (cntl_done) begin
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state <= 4'b1111;
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state <= 3'b111;
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wt <= 0;
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ack <= 1;
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end
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end
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end
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end
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4'b0011:
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3'b011:
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// read word, upper 16 bits
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// read word, upper 16 bits
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begin
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begin
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if (cntl_done == 1) begin
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if (cntl_done) begin
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state <= 4'b0100;
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state <= 3'b100;
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data_out[31:16] <= cntl_dout;
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data_out[31:16] <= cntl_dout;
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end
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end
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end
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end
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4'b0100:
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3'b100:
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// read word, lower 16 bits
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// read word, lower 16 bits
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begin
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begin
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if (cntl_done == 1) begin
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if (cntl_done) begin
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state <= 4'b1111;
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state <= 3'b111;
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data_out[15:0] <= cntl_dout;
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wt <= 0;
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end
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end
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4'b0101:
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// write halfword
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begin
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if (cntl_done == 1) begin
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state <= 4'b1111;
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wt <= 0;
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end
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end
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4'b0110:
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// read halfword
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begin
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if (cntl_done == 1) begin
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state <= 4'b1111;
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data_out[31:16] <= 16'h0000;
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data_out[15:0] <= cntl_dout;
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data_out[15:0] <= cntl_dout;
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wt <= 0;
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ack <= 1;
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end
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end
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4'b0111:
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// write byte (read halfword cycle)
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begin
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if (cntl_done == 1) begin
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state <= 4'b1000;
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data_out[31:16] <= 16'h0000;
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data_out[15:0] <= cntl_dout;
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end
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end
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4'b1000:
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// write byte (write halfword cycle)
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begin
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if (cntl_done == 1) begin
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state <= 4'b1111;
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wt <= 0;
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end
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end
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4'b1001:
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// read byte
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begin
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if (cntl_done == 1) begin
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state <= 4'b1111;
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data_out[31:8] <= 24'h000000;
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if (addr[0] == 0) begin
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data_out[7:0] <= cntl_dout[15:8];
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end else begin
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data_out[7:0] <= cntl_dout[7:0];
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end
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wt <= 0;
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end
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end
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end
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end
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4'b1111:
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3'b111:
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// end of bus cycle
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// end of bus cycle
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begin
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begin
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state <= 4'b0000;
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state <= 3'b000;
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wt <= 1;
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ack <= 0;
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end
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end
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default:
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default:
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// all other states: reset
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// all other states: reset
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begin
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begin
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state <= 4'b0000;
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state <= 3'b000;
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wt <= 1;
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ack <= 0;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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// output of state machine
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// output of state machine
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always @(*) begin
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always @(*) begin
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case (state)
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case (state)
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4'b0000:
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3'b000:
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// wait for access
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// wait for access
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begin
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begin
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a0 = 1'bx;
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a0 = 1'bx;
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cntl_read = 0;
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cntl_read = 0;
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cntl_write = 0;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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cntl_din = 16'hxxxx;
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end
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end
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4'b0001:
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3'b001:
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// write word, upper 16 bits
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// write word, upper 16 bits
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begin
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begin
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a0 = 1'b0;
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a0 = 1'b0;
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cntl_read = 0;
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cntl_read = 0;
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cntl_write = 1;
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cntl_write = 1;
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cntl_din = data_in[31:16];
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cntl_din = data_in[31:16];
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end
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end
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4'b0010:
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3'b010:
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// write word, lower 16 bits
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// write word, lower 16 bits
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begin
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begin
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a0 = 1'b1;
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a0 = 1'b1;
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cntl_read = 0;
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cntl_read = 0;
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cntl_write = 1;
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cntl_write = 1;
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cntl_din = data_in[15:0];
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cntl_din = data_in[15:0];
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end
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end
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4'b0011:
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3'b011:
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// read word, upper 16 bits
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// read word, upper 16 bits
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begin
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begin
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a0 = 1'b0;
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a0 = 1'b0;
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cntl_read = 1;
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cntl_read = 1;
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cntl_write = 0;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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cntl_din = 16'hxxxx;
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end
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end
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4'b0100:
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3'b100:
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// read word, lower 16 bits
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// read word, lower 16 bits
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begin
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begin
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a0 = 1'b1;
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a0 = 1'b1;
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cntl_read = 1;
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cntl_read = 1;
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cntl_write = 0;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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cntl_din = 16'hxxxx;
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end
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end
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4'b0101:
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3'b111:
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// write halfword
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begin
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a0 = addr[1];
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cntl_read = 0;
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cntl_write = 1;
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cntl_din = data_in[15:0];
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end
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4'b0110:
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// read halfword
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begin
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a0 = addr[1];
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cntl_read = 1;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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end
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4'b0111:
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// write byte (read halfword cycle)
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begin
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a0 = addr[1];
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cntl_read = 1;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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end
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4'b1000:
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// write byte (write halfword cycle)
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begin
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a0 = addr[1];
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cntl_read = 0;
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cntl_write = 1;
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if (addr[0] == 0) begin
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cntl_din = { data_in[7:0], data_out[7:0] };
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end else begin
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cntl_din = { data_out[15:8], data_in[7:0] };
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end
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end
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4'b1001:
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// read byte
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begin
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a0 = addr[1];
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cntl_read = 1;
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cntl_write = 0;
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cntl_din = 16'hxxxx;
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end
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4'b1111:
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// end of bus cycle
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// end of bus cycle
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begin
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begin
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a0 = 1'bx;
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a0 = 1'bx;
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cntl_read = 0;
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cntl_read = 0;
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cntl_write = 0;
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cntl_write = 0;
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