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//
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// ram.v -- main memory, using SDRAM
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//
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module ram(clk, clk_ok, reset,
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module ram(clk, clk_ok, reset,
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en, wr, size, addr,
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en, wr, size, addr,
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data_in, data_out, wt,
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data_in, data_out, wt,
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sdram_cke, sdram_cs_n,
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sdram_cke, sdram_cs_n,
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sdram_udqm, sdram_ldqm,
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sdram_udqm, sdram_ldqm,
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sdram_ras_n, sdram_cas_n,
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sdram_ras_n, sdram_cas_n,
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sdram_we_n, sdram_ba,
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sdram_we_n, sdram_ba,
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sdram_a, sdram_dq);
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sdram_a, sdram_dq);
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// internal interface signals
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input clk;
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input clk;
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input clk_ok;
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input clk_ok;
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input reset;
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input reset;
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input en;
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input en;
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input wr;
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input wr;
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input [1:0] size;
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input [1:0] size;
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input [24:0] addr;
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input [24:0] addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output reg [31:0] data_out;
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output reg [31:0] data_out;
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output reg wt;
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output reg wt;
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// SDRAM interface signals
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output sdram_cke;
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output sdram_cke;
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output sdram_cs_n;
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output sdram_cs_n;
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output sdram_udqm;
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output sdram_udqm;
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output sdram_ldqm;
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output sdram_ldqm;
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output sdram_ras_n;
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output sdram_ras_n;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// the SDRAM is organized in 16-bit halfwords
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// the SDRAM is organized in 16-bit halfwords
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// address line 0 is controlled by the state machine
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// address line 0 is controlled by the state machine
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// this is necessary for word accesses
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// (this is necessary for word accesses)
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assign cntl_addr[23:1] = addr[24:2];
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assign cntl_addr[23:1] = addr[24:2];
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assign cntl_addr[0] = a0;
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assign cntl_addr[0] = a0;
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// state machine for SDRAM access
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// state machine for SDRAM access
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always @(posedge clk) begin
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always @(posedge clk) begin
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