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//
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//
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// rom.v -- parallel flash ROM interface
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// rom.v -- parallel flash ROM interface
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// 4M x 32 bit = 16 MB
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//
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//
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module rom(clk, reset,
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`timescale 1ns/10ps
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en, wr, size, addr,
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`default_nettype none
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data_out, wt, spi_en,
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module rom(clk, rst,
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stb, we, addr,
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data_out, ack, spi_en,
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ce_n, oe_n, we_n, byte_n, a, d);
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ce_n, oe_n, we_n, byte_n, a, d);
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// internal interface signals
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// internal interface signals
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input clk;
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input clk;
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input reset;
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input rst;
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input en;
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input stb;
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input wr;
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input we;
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input [1:0] size;
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input [23:2] addr;
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input [23:0] addr;
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output reg [31:0] data_out;
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output reg [31:0] data_out;
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output reg wt;
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output reg ack;
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input spi_en;
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input spi_en;
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// flash ROM interface signals
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// flash ROM interface signals
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output ce_n;
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output ce_n;
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output oe_n;
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output oe_n;
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output we_n;
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output we_n;
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assign we_n = 1;
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assign we_n = 1;
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assign byte_n = 1;
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assign byte_n = 1;
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// the flash ROM is organized in 16-bit halfwords
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// the flash ROM is organized in 16-bit halfwords
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// address line a[1] is controlled by the state machine
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// address line a[1] is controlled by the state machine
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// (this is necessary for word accesses)
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// ("upper half" means "at higher address in ROM")
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// address line a[0] is not used
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// address line a[0] is not used
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// (it controls high/low byte select in byte mode)
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// (it controls high/low byte select in byte mode)
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assign a[23:2] = addr[23:2];
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assign a[23:2] = addr[23:2];
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assign a[1] = upper_half;
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assign a[1] = upper_half;
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assign a[0] = 0;
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assign a[0] = 0;
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// the state machine
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// the state machine
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (rst) begin
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state <= 0;
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state <= 0;
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wt <= 1;
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ack <= 0;
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end else begin
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end else begin
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if (state == 0) begin
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if (state == 0) begin
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// wait for start of access
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// wait for start of access
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if (en == 1 && wr == 0) begin
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if (stb & ~we) begin
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state <= 1;
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state <= 1;
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if (size[1] == 1) begin
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// word access
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upper_half <= 0;
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upper_half <= 0;
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end else begin
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// halfword or byte access
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upper_half <= addr[1];
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end
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end
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end
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end else
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end else
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if (state == 6) begin
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if (state == 6) begin
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if (size[1] == 1) begin
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// word access
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// latch upper halfword
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// latch upper halfword
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data_out[31:24] <= d[7:0];
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data_out[31:24] <= d[7:0];
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data_out[23:16] <= d[15:8];
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data_out[23:16] <= d[15:8];
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state <= 7;
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state <= 7;
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upper_half <= 1;
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upper_half <= 1;
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end else begin
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// halfword or byte access
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data_out[31:16] <= 16'h0000;
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if (size[0] == 1) begin
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// halfword access
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data_out[15:8] <= d[7:0];
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data_out[7:0] <= d[15:8];
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end else begin
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// byte access
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data_out[15:8] <= 8'h00;
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if (addr[0] == 0) begin
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// even address
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data_out[7:0] <= d[7:0];
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end else begin
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// odd address
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data_out[7:0] <= d[15:8];
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end
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end
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state <= 13;
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wt <= 0;
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end
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end else
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end else
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if (state == 12) begin
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if (state == 12) begin
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// word access (state is only reached in this case)
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// latch lower halfword
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// latch lower halfword
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data_out[15:8] <= d[7:0];
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data_out[15:8] <= d[7:0];
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data_out[7:0] <= d[15:8];
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data_out[7:0] <= d[15:8];
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state <= 13;
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state <= 13;
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wt <= 0;
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ack <= 1;
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end else
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end else
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if (state == 13) begin
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if (state == 13) begin
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// end of access
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// end of access
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wt <= 1;
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ack <= 0;
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state <= 0;
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state <= 0;
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end else begin
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end else begin
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// wait for flash ROM access time to pass
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// wait for flash ROM access time to pass
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state <= state + 1;
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state <= state + 1;
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end
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end
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