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| Rev 118 |
Rev 220 |
| Line 24... |
Line 24... |
output byte_n;
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output byte_n;
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output [19:0] a;
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output [19:0] a;
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input [15:0] d;
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input [15:0] d;
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reg [3:0] state;
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reg [3:0] state;
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reg a0;
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reg upper_half;
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// the following control signals are all
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// the following control signals are all
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// either constantly asserted or deasserted
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// either constantly asserted or deasserted
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assign ce_n = 0;
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assign ce_n = 0;
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assign oe_n = 0;
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assign oe_n = 0;
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assign we_n = 1;
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assign we_n = 1;
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assign rst_n = 1;
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assign rst_n = 1;
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assign byte_n = 1;
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assign byte_n = 1;
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// the flash ROM is organized in 16-bit halfwords
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// the flash ROM is organized in 16-bit halfwords
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// address line a0 is controlled by the state machine
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// address line a[0] is controlled by the state machine
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// (this is necessary for word accesses)
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// (this is necessary for word accesses)
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assign a[19:1] = addr[20:2];
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assign a[19:1] = addr[20:2];
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assign a[0] = a0;
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assign a[0] = upper_half;
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// the state machine
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// the state machine
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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state <= 0;
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state <= 0;
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| Line 52... |
Line 52... |
// wait for start of access
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// wait for start of access
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if (en == 1 && wr == 0) begin
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if (en == 1 && wr == 0) begin
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state <= 1;
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state <= 1;
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if (size[1] == 1) begin
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if (size[1] == 1) begin
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// word access
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// word access
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a0 <= 0;
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upper_half <= 0;
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end else begin
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end else begin
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// halfword or byte access
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// halfword or byte access
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a0 <= addr[1];
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upper_half <= addr[1];
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end
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end
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end
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end
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end else
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end else
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if (state == 6) begin
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if (state == 6) begin
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if (size[1] == 1) begin
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if (size[1] == 1) begin
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// word access
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// word access
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// latch upper halfword
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// latch upper halfword
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data_out[31:24] <= d[7:0];
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data_out[31:24] <= d[7:0];
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data_out[23:16] <= d[15:8];
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data_out[23:16] <= d[15:8];
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state <= 7;
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state <= 7;
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a0 <= 1;
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upper_half <= 1;
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end else begin
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end else begin
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// halfword or byte access
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// halfword or byte access
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data_out[31:16] <= 16'h0000;
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data_out[31:16] <= 16'h0000;
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if (size[0] == 1) begin
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if (size[0] == 1) begin
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// halfword access
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// halfword access
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