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//
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//
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// ser.v -- serial line interface
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// ser.v -- serial line interface
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//
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//
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module ser(clk, reset,
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`timescale 1ns/10ps
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en, wr, addr,
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`default_nettype none
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module ser(clk, rst,
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stb, we, addr,
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data_in, data_out,
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data_in, data_out,
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wt, irq_r, irq_t,
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ack, irq_r, irq_t,
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rxd, txd);
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rxd, txd);
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// internal interface
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// internal interface
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input clk;
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input clk;
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input reset;
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input rst;
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input en;
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input stb;
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input wr;
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input we;
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input [3:2] addr;
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input [3:2] addr;
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input [7:0] data_in;
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input [7:0] data_in;
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output reg [7:0] data_out;
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output reg [7:0] data_out;
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output wt;
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output ack;
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output irq_r;
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output irq_r;
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output irq_t;
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output irq_t;
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// external interface
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// external interface
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input rxd;
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input rxd;
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output txd;
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output txd;
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wire wr_rcv_ctrl;
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wire wr_rcv_ctrl;
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wire rd_rcv_data;
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wire rd_rcv_data;
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wire wr_xmt_ctrl;
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wire wr_xmt_ctrl;
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wire wr_xmt_data;
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wire wr_xmt_data;
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wire rcv_ready;
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wire rcv_rdy;
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reg rcv_ien;
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reg rcv_ien;
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wire [7:0] rcv_data;
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wire [7:0] rcv_data;
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wire xmt_ready;
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wire xmt_rdy;
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reg xmt_ien;
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reg xmt_ien;
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assign wr_rcv_ctrl = (en == 1 && wr == 1 && addr == 2'b00) ? 1 : 0;
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assign wr_rcv_ctrl = (stb == 1 && we == 1 && addr == 2'b00) ? 1 : 0;
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assign rd_rcv_data = (en == 1 && wr == 0 && addr == 2'b01) ? 1 : 0;
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assign rd_rcv_data = (stb == 1 && we == 0 && addr == 2'b01) ? 1 : 0;
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assign wr_xmt_ctrl = (en == 1 && wr == 1 && addr == 2'b10) ? 1 : 0;
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assign wr_xmt_ctrl = (stb == 1 && we == 1 && addr == 2'b10) ? 1 : 0;
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assign wr_xmt_data = (en == 1 && wr == 1 && addr == 2'b11) ? 1 : 0;
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assign wr_xmt_data = (stb == 1 && we == 1 && addr == 2'b11) ? 1 : 0;
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rcvbuf rcvbuf1(clk, reset, rd_rcv_data, rcv_ready, rcv_data, rxd);
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rcvbuf rcvbuf_1(clk, rst, rd_rcv_data, rcv_rdy, rcv_data, rxd);
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xmtbuf xmtbuf1(clk, reset, wr_xmt_data, xmt_ready, data_in, txd);
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xmtbuf xmtbuf_1(clk, rst, wr_xmt_data, xmt_rdy, data_in, txd);
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (rst) begin
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rcv_ien <= 0;
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rcv_ien <= 0;
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xmt_ien <= 0;
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xmt_ien <= 0;
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end else begin
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end else begin
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if (wr_rcv_ctrl) begin
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if (wr_rcv_ctrl) begin
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rcv_ien <= data_in[1];
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rcv_ien <= data_in[1];
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always @(*) begin
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always @(*) begin
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case (addr[3:2])
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case (addr[3:2])
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2'b00:
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2'b00:
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// rcv ctrl
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// rcv ctrl
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data_out = { 6'b000000, rcv_ien, rcv_ready };
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data_out = { 6'b000000, rcv_ien, rcv_rdy };
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2'b01:
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2'b01:
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// rcv data
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// rcv data
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data_out = rcv_data;
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data_out = rcv_data;
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2'b10:
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2'b10:
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// xmt ctrl
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// xmt ctrl
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data_out = { 6'b000000, xmt_ien, xmt_ready };
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data_out = { 6'b000000, xmt_ien, xmt_rdy };
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2'b11:
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2'b11:
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// xmt data (cannot be read)
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// xmt data (cannot be read)
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data_out = 8'hxx;
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data_out = 8'hxx;
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default:
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default:
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data_out = 8'hxx;
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data_out = 8'hxx;
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endcase
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endcase
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end
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end
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assign wt = 1'b0;
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assign ack = stb;
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assign irq_r = rcv_ien & rcv_ready;
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assign irq_r = rcv_ien & rcv_rdy;
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assign irq_t = xmt_ien & xmt_ready;
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assign irq_t = xmt_ien & xmt_rdy;
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endmodule
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endmodule
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