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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [tmr/] [tmr.v] - Diff between revs 288 and 290

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//
 
//
 
// tmr.v -- programmable timer
 
// tmr.v -- programmable timer
 
//
 
//
 
 
 
 
 
 
 
 
 
module tmr(clk, reset,
 
`timescale 1ns/10ps
 
           en, wr, addr,
 
`default_nettype none
 
 
 
 
 
 
 
 
 
 
 
module tmr(clk, rst,
 
 
 
           stb, we, addr,
 
           data_in, data_out,
 
           data_in, data_out,
 
           wt, irq);
 
           ack, irq);
 
    input clk;
 
    input clk;
 
    input reset;
 
    input rst;
 
    input en;
 
    input stb;
 
    input wr;
 
    input we;
 
    input [3:2] addr;
 
    input [3:2] addr;
 
    input [31:0] data_in;
 
    input [31:0] data_in;
 
    output reg [31:0] data_out;
 
    output reg [31:0] data_out;
 
    output wt;
 
    output ack;
 
    output irq;
 
    output irq;
 
 
 
 
 
  reg [31:0] counter;
 
  reg [31:0] counter;
 
  reg [31:0] divisor;
 
  reg [31:0] divisor;
 
  reg divisor_loaded;
 
  reg divisor_loaded;
 
  reg expired;
 
  reg expired;
 
  reg alarm;
 
  reg alarm;
 
  reg ien;
 
  reg ien;
 
 
 
 
 
  always @(posedge clk) begin
 
  always @(posedge clk) begin
 
    if (divisor_loaded == 1) begin
 
    if (divisor_loaded) begin
 
      counter <= divisor;
 
      counter <= divisor;
 
      expired <= 0;
 
      expired <= 0;
 
    end else begin
 
    end else begin
 
      if (counter == 32'h00000001) begin
 
      if (counter == 32'h00000001) begin
 
        counter <= divisor;
 
        counter <= divisor;
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      end
 
      end
 
    end
 
    end
 
  end
 
  end
 
 
 
 
 
  always @(posedge clk) begin
 
  always @(posedge clk) begin
 
    if (reset == 1) begin
 
    if (rst) begin
 
      divisor <= 32'hFFFFFFFF;
 
      divisor <= 32'hFFFFFFFF;
 
      divisor_loaded <= 1;
 
      divisor_loaded <= 1;
 
      alarm <= 0;
 
      alarm <= 0;
 
      ien <= 0;
 
      ien <= 0;
 
    end else begin
 
    end else begin
 
      if (expired == 1) begin
 
      if (expired) begin
 
        alarm <= 1;
 
        alarm <= 1;
 
      end else begin
 
      end else begin
 
        if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
 
        if (stb == 1 && we == 1 && addr[3:2] == 2'b00) begin
 
 
 
          // ctrl
 
          alarm <= data_in[0];
 
          alarm <= data_in[0];
 
          ien <= data_in[1];
 
          ien <= data_in[1];
 
        end
 
        end
 
        if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
 
        if (stb == 1 && we == 1 && addr[3:2] == 2'b01) begin
 
 
 
          // divisor
 
          divisor <= data_in;
 
          divisor <= data_in;
 
          divisor_loaded <= 1;
 
          divisor_loaded <= 1;
 
        end else begin
 
        end else begin
 
          divisor_loaded <= 0;
 
          divisor_loaded <= 0;
 
        end
 
        end
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      default:
 
      default:
 
        data_out = 32'hxxxxxxxx;
 
        data_out = 32'hxxxxxxxx;
 
    endcase
 
    endcase
 
  end
 
  end
 
 
 
 
 
  assign wt = 0;
 
  assign ack = stb;
 
  assign irq = ien & alarm;
 
  assign irq = ien & alarm;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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