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//
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// tmr.v -- programmable timer
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//
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module tmr(clk, reset,
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module tmr(clk, reset,
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en, wr, addr,
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en, wr, addr,
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data_in, data_out,
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data_in, data_out,
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wt, irq);
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wt, irq);
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input clk;
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input clk;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output [31:0] data_out;
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output wt;
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output wt;
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output irq;
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output irq;
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reg [15:0] prescaler;
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reg [5:0] prescaler;
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reg tick;
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reg tick;
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reg [31:0] counter;
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reg [31:0] counter;
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reg [31:0] divisor;
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reg [31:0] divisor;
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reg divisor_loaded;
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reg divisor_loaded;
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reg expired;
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reg expired;
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reg alarm;
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reg alarm;
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reg ien;
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reg ien;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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prescaler <= 16'd50000;
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prescaler <= 6'd50;
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tick <= 0;
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tick <= 0;
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end else begin
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end else begin
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if (prescaler == 16'd1) begin
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if (prescaler == 6'd1) begin
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prescaler <= 16'd50000;
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prescaler <= 6'd50;
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tick <= 1;
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tick <= 1;
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end else begin
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end else begin
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prescaler <= prescaler - 1;
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prescaler <= prescaler - 1;
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tick <= 0;
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tick <= 0;
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end
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end
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