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https://opencores.org/ocsvn/eco32/eco32/trunk
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| Rev 68 |
Rev 69 |
| Line 9... |
Line 9... |
wt, irq);
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wt, irq);
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input clk;
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input clk;
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input reset;
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input reset;
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input en;
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input en;
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input wr;
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input wr;
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input addr;
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input [3:2] addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output reg [31:0] data_out;
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output wt;
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output wt;
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output irq;
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output irq;
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reg [5:0] prescaler;
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reg tick;
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reg [31:0] counter;
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reg [31:0] counter;
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reg [31:0] divisor;
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reg [31:0] divisor;
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reg divisor_loaded;
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reg divisor_loaded;
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reg expired;
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reg expired;
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reg alarm;
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reg alarm;
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reg ien;
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reg ien;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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prescaler <= 6'd50;
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tick <= 0;
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end else begin
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if (prescaler == 6'd1) begin
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prescaler <= 6'd50;
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tick <= 1;
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end else begin
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prescaler <= prescaler - 1;
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tick <= 0;
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end
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end
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end
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always @(posedge clk) begin
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if (divisor_loaded == 1) begin
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if (divisor_loaded == 1) begin
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counter <= divisor;
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counter <= divisor;
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expired <= 0;
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expired <= 0;
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end else begin
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end else begin
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if (tick == 1) begin
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if (counter == 32'h00000001) begin
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if (counter == 32'h00000001) begin
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counter <= divisor;
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counter <= divisor;
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expired <= 1;
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expired <= 1;
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end else begin
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end else begin
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counter <= counter - 1;
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counter <= counter - 1;
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expired <= 0;
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expired <= 0;
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end
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end
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end else begin
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expired <= 0;
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1) begin
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if (reset == 1) begin
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| Line 68... |
Line 47... |
ien <= 0;
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ien <= 0;
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end else begin
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end else begin
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if (expired == 1) begin
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if (expired == 1) begin
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alarm <= 1;
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alarm <= 1;
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end else begin
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end else begin
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if (en == 1 && wr == 1 && addr == 0) begin
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if (en == 1 && wr == 1 && addr[3:2] == 2'b00) begin
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alarm <= data_in[0];
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alarm <= data_in[0];
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ien <= data_in[1];
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ien <= data_in[1];
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end
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end
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if (en == 1 && wr == 1 && addr == 1) begin
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if (en == 1 && wr == 1 && addr[3:2] == 2'b01) begin
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divisor <= data_in;
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divisor <= data_in;
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divisor_loaded <= 1;
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divisor_loaded <= 1;
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end else begin
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end else begin
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divisor_loaded <= 0;
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divisor_loaded <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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assign data_out =
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always @(*) begin
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(addr == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
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case (addr[3:2])
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divisor;
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2'b00:
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// ctrl
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data_out = { 28'h0000000, 2'b00, ien, alarm };
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2'b01:
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// divisor
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data_out = divisor;
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2'b10:
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// counter
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data_out = counter;
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2'b11:
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// not used
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data_out = 32'hxxxxxxxx;
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default:
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data_out = 32'hxxxxxxxx;
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endcase
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end
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assign wt = 0;
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assign wt = 0;
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assign irq = ien & alarm;
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assign irq = ien & alarm;
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endmodule
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endmodule
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