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[/] [eco32/] [trunk/] [fpga/] [mc-vl/] [main.cpp] - Diff between revs 309 and 310
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/*
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/*
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* main.cpp -- simulation control
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* main.cpp -- simulation control
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*/
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*/
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#if VM_TRACE
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#define VCD_NAME "dump.vcd"
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#endif
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#define DURATION_NAME "duration.dat" /* simulation duration file name */
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#define RST_IN_OFF 145 /* trailing edge of rst_in, in ns */
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#define HALF_PERIOD 10 /* half of clock period, in ns */
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#include <iostream>
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#include <fstream>
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using namespace std;
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#include "Veco32test.h"
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#include "Veco32test.h"
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#include "verilated.h"
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#include "verilated.h"
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#if VM_TRACE
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#include "verilated_vcd_c.h"
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#endif
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int main(int argc, char *argv[]) {
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int main(int argc, char *argv[]) {
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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Veco32test *top = new Veco32test;
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Veco32test *top = new Veco32test;
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vluint64_t numHalfCycles = 0;
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#if VM_TRACE
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top->clk_in = 0;
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Verilated::traceEverOn(true);
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VerilatedVcdC *tfp = new VerilatedVcdC;
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top->trace(tfp, 99);
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tfp->open(VCD_NAME);
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#endif
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ifstream durationFile(DURATION_NAME);
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if (!durationFile.is_open()) {
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cout << "Error: cannot open input file '"
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<< DURATION_NAME
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<< "'\n";
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abort();
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}
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vluint64_t maxTime;
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durationFile >> maxTime;
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maxTime += RST_IN_OFF;
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durationFile.close();
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vluint64_t curTime = 0;
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top->clk_in = 1;
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top->rst_in_n = 0;
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top->rst_in_n = 0;
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while (numHalfCycles < 2 * 30000000) {
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while (curTime <= maxTime) {
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if (numHalfCycles == 2 * 145) {
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if (top->rst_in_n == 0 && curTime >= RST_IN_OFF) {
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top->rst_in_n = 1;
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top->rst_in_n = 1;
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}
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}
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top->eval();
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top->eval();
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#if VM_TRACE
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tfp->dump(curTime);
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#endif
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top->clk_in = !top->clk_in;
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top->clk_in = !top->clk_in;
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numHalfCycles++;
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curTime += HALF_PERIOD;
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}
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}
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top->final();
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top->final();
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#if VM_TRACE
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tfp->close();
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delete tfp;
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#endif
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delete top;
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delete top;
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return 0;
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return 0;
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}
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}
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