| Line 12... |
Line 12... |
.set TLB_INDEX,1 ; reg # of TLB Index
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.set TLB_INDEX,1 ; reg # of TLB Index
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.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
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.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
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.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
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.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
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.set TLB_ENTRIES,32 ; number of TLB entries
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.set TLB_ENTRIES,32 ; number of TLB entries
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.set BAD_ADDRESS,4 ; reg # of bad address reg
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.set BAD_ADDRESS,4 ; reg # of bad address reg
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.set BAD_ACCESS,5 ; reg # of bad access reg
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.set USER_CONTEXT_SIZE,37*4 ; size of user context
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.set USER_CONTEXT_SIZE,38*4 ; size of user context
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.set BIO_OUT,0xF1000000 ; board I/O output port
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.set BIO_OUT,0xF1000000 ; board I/O output port
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.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit
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.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit
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;***************************************************************
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;***************************************************************
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| Line 364... |
Line 365... |
mvts $8,TLB_ENTRY_HI
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mvts $8,TLB_ENTRY_HI
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ldw $8,$28,35*4 ; tlbEntryLo
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ldw $8,$28,35*4 ; tlbEntryLo
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mvts $8,TLB_ENTRY_LO
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mvts $8,TLB_ENTRY_LO
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ldw $8,$28,36*4 ; badAddress
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ldw $8,$28,36*4 ; badAddress
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mvts $8,BAD_ADDRESS
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mvts $8,BAD_ADDRESS
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ldw $8,$28,37*4 ; badAccess
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mvts $8,BAD_ACCESS
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;ldw $0,$28,0*4 ; registers
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;ldw $0,$28,0*4 ; registers
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ldw $1,$28,1*4
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ldw $1,$28,1*4
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ldw $2,$28,2*4
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ldw $2,$28,2*4
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ldw $3,$28,3*4
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ldw $3,$28,3*4
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ldw $4,$28,4*4
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ldw $4,$28,4*4
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| Line 450... |
Line 453... |
stw $8,$28,34*4 ; tlbEntryHi
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stw $8,$28,34*4 ; tlbEntryHi
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mvfs $8,TLB_ENTRY_LO
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mvfs $8,TLB_ENTRY_LO
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stw $8,$28,35*4 ; tlbEntryLo
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stw $8,$28,35*4 ; tlbEntryLo
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mvfs $8,BAD_ADDRESS
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mvfs $8,BAD_ADDRESS
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stw $8,$28,36*4 ; badAddress
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stw $8,$28,36*4 ; badAddress
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mvfs $8,BAD_ACCESS
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stw $8,$28,37*4 ; badAccess
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.syn
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.syn
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j loadState
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j loadState
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No newline at end of file
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No newline at end of file
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