| Line 12... |
Line 12... |
#include "console.h"
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#include "console.h"
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#include "error.h"
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#include "error.h"
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#include "except.h"
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#include "except.h"
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#include "instr.h"
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#include "instr.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "trace.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "timer.h"
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#include "timer.h"
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/**************************************************************/
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/**************************************************************/
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| Line 86... |
Line 87... |
break;
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break;
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}
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}
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}
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}
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/* acknowledge exception, or interrupt if enabled */
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/* acknowledge exception, or interrupt if enabled */
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if (priority >= 16 || IE != 0) {
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if (priority >= 16 || IE != 0) {
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traceException(priority);
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if (priority >= 16) {
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if (priority >= 16) {
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/* clear corresponding bit in irqPending vector */
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/* clear corresponding bit in irqPending vector */
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/* only done for exceptions, since interrupts are level-sensitive */
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/* only done for exceptions, since interrupts are level-sensitive */
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irqPending &= ~((unsigned) 1 << priority);
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irqPending &= ~((unsigned) 1 << priority);
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}
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}
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| Line 148... |
Line 150... |
Half immed;
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Half immed;
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Word offset;
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Word offset;
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int scnt;
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int scnt;
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Word smsk;
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Word smsk;
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Word aux;
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Word aux;
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Word addr;
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/* count the instruction */
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/* count the instruction */
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total++;
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total++;
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/* fetch the instruction */
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/* fetch the instruction */
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traceFetch(pc);
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instr = mmuReadWord(pc, UM);
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instr = mmuReadWord(pc, UM);
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traceExec(instr, pc);
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/* decode the instruction */
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/* decode the instruction */
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op = (instr >> 26) & 0x3F;
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op = (instr >> 26) & 0x3F;
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reg1 = (instr >> 21) & 0x1F;
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reg1 = (instr >> 21) & 0x1F;
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reg2 = (instr >> 16) & 0x1F;
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reg2 = (instr >> 16) & 0x1F;
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reg3 = (instr >> 11) & 0x1F;
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reg3 = (instr >> 11) & 0x1F;
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| Line 383... |
Line 388... |
psw &= ~PSW_PUM;
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psw &= ~PSW_PUM;
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}
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}
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next = RR(30);
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next = RR(30);
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break;
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break;
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case OP_LDW:
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case OP_LDW:
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WR(reg2, mmuReadWord(RR(reg1) + SEXT16(immed), UM));
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addr = RR(reg1) + SEXT16(immed);
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traceLoadWord(addr);
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WR(reg2, mmuReadWord(addr, UM));
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break;
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break;
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case OP_LDH:
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case OP_LDH:
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WR(reg2, (signed int) (signed short)
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addr = RR(reg1) + SEXT16(immed);
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mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
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traceLoadHalf(addr);
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WR(reg2, (signed int) (signed short) mmuReadHalf(addr, UM));
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break;
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break;
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case OP_LDHU:
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case OP_LDHU:
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WR(reg2, mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
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addr = RR(reg1) + SEXT16(immed);
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traceLoadHalf(addr);
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WR(reg2, mmuReadHalf(addr, UM));
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break;
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break;
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case OP_LDB:
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case OP_LDB:
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WR(reg2, (signed int) (signed char)
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addr = RR(reg1) + SEXT16(immed);
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mmuReadByte(RR(reg1) + SEXT16(immed), UM));
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traceLoadByte(addr);
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WR(reg2, (signed int) (signed char) mmuReadByte(addr, UM));
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break;
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break;
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case OP_LDBU:
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case OP_LDBU:
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WR(reg2, mmuReadByte(RR(reg1) + SEXT16(immed), UM));
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addr = RR(reg1) + SEXT16(immed);
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traceLoadByte(addr);
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WR(reg2, mmuReadByte(addr, UM));
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break;
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break;
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case OP_STW:
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case OP_STW:
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mmuWriteWord(RR(reg1) + SEXT16(immed), RR(reg2), UM);
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addr = RR(reg1) + SEXT16(immed);
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traceStoreWord(addr);
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mmuWriteWord(addr, RR(reg2), UM);
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break;
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break;
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case OP_STH:
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case OP_STH:
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mmuWriteHalf(RR(reg1) + SEXT16(immed), RR(reg2), UM);
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addr = RR(reg1) + SEXT16(immed);
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traceStoreHalf(addr);
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mmuWriteHalf(addr, RR(reg2), UM);
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break;
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break;
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case OP_STB:
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case OP_STB:
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mmuWriteByte(RR(reg1) + SEXT16(immed), RR(reg2), UM);
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addr = RR(reg1) + SEXT16(immed);
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traceStoreByte(addr);
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mmuWriteByte(addr, RR(reg2), UM);
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break;
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break;
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case OP_MVFS:
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case OP_MVFS:
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switch (immed) {
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switch (immed) {
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case 0:
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case 0:
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WR(reg2, psw);
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WR(reg2, psw);
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