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Subversion Repositories eco32

[/] [eco32/] [trunk/] [sim/] [cpu.c] - Diff between revs 168 and 275

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Rev 168 Rev 275
Line 12... Line 12...
#include "console.h"
#include "console.h"
#include "error.h"
#include "error.h"
#include "except.h"
#include "except.h"
#include "instr.h"
#include "instr.h"
#include "cpu.h"
#include "cpu.h"
 
#include "trace.h"
#include "mmu.h"
#include "mmu.h"
#include "timer.h"
#include "timer.h"
 
 
 
 
/**************************************************************/
/**************************************************************/
Line 86... Line 87...
      break;
      break;
    }
    }
  }
  }
  /* acknowledge exception, or interrupt if enabled */
  /* acknowledge exception, or interrupt if enabled */
  if (priority >= 16 || IE != 0) {
  if (priority >= 16 || IE != 0) {
 
    traceException(priority);
    if (priority >= 16) {
    if (priority >= 16) {
      /* clear corresponding bit in irqPending vector */
      /* clear corresponding bit in irqPending vector */
      /* only done for exceptions, since interrupts are level-sensitive */
      /* only done for exceptions, since interrupts are level-sensitive */
      irqPending &= ~((unsigned) 1 << priority);
      irqPending &= ~((unsigned) 1 << priority);
    }
    }
Line 148... Line 150...
  Half immed;
  Half immed;
  Word offset;
  Word offset;
  int scnt;
  int scnt;
  Word smsk;
  Word smsk;
  Word aux;
  Word aux;
 
  Word addr;
 
 
  /* count the instruction */
  /* count the instruction */
  total++;
  total++;
  /* fetch the instruction */
  /* fetch the instruction */
 
  traceFetch(pc);
  instr = mmuReadWord(pc, UM);
  instr = mmuReadWord(pc, UM);
 
  traceExec(instr, pc);
  /* decode the instruction */
  /* decode the instruction */
  op = (instr >> 26) & 0x3F;
  op = (instr >> 26) & 0x3F;
  reg1 = (instr >> 21) & 0x1F;
  reg1 = (instr >> 21) & 0x1F;
  reg2 = (instr >> 16) & 0x1F;
  reg2 = (instr >> 16) & 0x1F;
  reg3 = (instr >> 11) & 0x1F;
  reg3 = (instr >> 11) & 0x1F;
Line 383... Line 388...
        psw &= ~PSW_PUM;
        psw &= ~PSW_PUM;
      }
      }
      next = RR(30);
      next = RR(30);
      break;
      break;
    case OP_LDW:
    case OP_LDW:
      WR(reg2, mmuReadWord(RR(reg1) + SEXT16(immed), UM));
      addr = RR(reg1) + SEXT16(immed);
 
      traceLoadWord(addr);
 
      WR(reg2, mmuReadWord(addr, UM));
      break;
      break;
    case OP_LDH:
    case OP_LDH:
      WR(reg2, (signed int) (signed short)
      addr = RR(reg1) + SEXT16(immed);
               mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
      traceLoadHalf(addr);
 
      WR(reg2, (signed int) (signed short) mmuReadHalf(addr, UM));
      break;
      break;
    case OP_LDHU:
    case OP_LDHU:
      WR(reg2, mmuReadHalf(RR(reg1) + SEXT16(immed), UM));
      addr = RR(reg1) + SEXT16(immed);
 
      traceLoadHalf(addr);
 
      WR(reg2, mmuReadHalf(addr, UM));
      break;
      break;
    case OP_LDB:
    case OP_LDB:
      WR(reg2, (signed int) (signed char)
      addr = RR(reg1) + SEXT16(immed);
               mmuReadByte(RR(reg1) + SEXT16(immed), UM));
      traceLoadByte(addr);
 
      WR(reg2, (signed int) (signed char) mmuReadByte(addr, UM));
      break;
      break;
    case OP_LDBU:
    case OP_LDBU:
      WR(reg2, mmuReadByte(RR(reg1) + SEXT16(immed), UM));
      addr = RR(reg1) + SEXT16(immed);
 
      traceLoadByte(addr);
 
      WR(reg2, mmuReadByte(addr, UM));
      break;
      break;
    case OP_STW:
    case OP_STW:
      mmuWriteWord(RR(reg1) + SEXT16(immed), RR(reg2), UM);
      addr = RR(reg1) + SEXT16(immed);
 
      traceStoreWord(addr);
 
      mmuWriteWord(addr, RR(reg2), UM);
      break;
      break;
    case OP_STH:
    case OP_STH:
      mmuWriteHalf(RR(reg1) + SEXT16(immed), RR(reg2), UM);
      addr = RR(reg1) + SEXT16(immed);
 
      traceStoreHalf(addr);
 
      mmuWriteHalf(addr, RR(reg2), UM);
      break;
      break;
    case OP_STB:
    case OP_STB:
      mmuWriteByte(RR(reg1) + SEXT16(immed), RR(reg2), UM);
      addr = RR(reg1) + SEXT16(immed);
 
      traceStoreByte(addr);
 
      mmuWriteByte(addr, RR(reg2), UM);
      break;
      break;
    case OP_MVFS:
    case OP_MVFS:
      switch (immed) {
      switch (immed) {
        case 0:
        case 0:
          WR(reg2, psw);
          WR(reg2, psw);

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