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## Generated SDC file "fpmult.sdc"

#************************************************************

## Copyright (C) 1991-2010 Altera Corporation

# Copyright (C) 1991-2010 Altera Corporation

## Your use of Altera Corporation's design tools, logic functions

# Your use of Altera Corporation's design tools, logic functions

## and other software and tools, and its AMPP partner logic

# and other software and tools, and its AMPP partner logic

## functions, and any output files from any of the foregoing

# functions, and any output files from any of the foregoing

## (including device programming or simulation files), and any

# (including device programming or simulation files), and any

## associated documentation or information are expressly subject

# associated documentation or information are expressly subject

## to the terms and conditions of the Altera Program License

# to the terms and conditions of the Altera Program License

## Subscription Agreement, Altera MegaCore Function License

# Subscription Agreement, Altera MegaCore Function License

## Agreement, or other applicable license agreement, including,

# Agreement, or other applicable license agreement, including,

## without limitation, that your use is for the sole purpose of

# without limitation, that your use is for the sole purpose of

## programming logic devices manufactured by Altera and sold by

# programming logic devices manufactured by Altera and sold by

## Altera or its authorized distributors.  Please refer to the

# Altera or its authorized distributors.  Please refer to the

## applicable agreement for further details.

# applicable agreement for further details.

## DATE    "Sun Jan 30 18:51:15 2011"

# Clock constraints

##

create_clock -name "clk" -period 50.000ns [get_ports {clk}] -waveform {0.000 25.000}

#**************************************************************

# Automatically constrain PLL and other generated clocks

# Time Information

derive_pll_clocks -create_base_clocks

set_time_format -unit ns -decimal_places 3

# Automatically calculate clock uncertainty to jitter and other effects.

#**************************************************************

set_output_delay -clock "clk" -max 40ns [get_ports {q.a q.b}]

# tpd constraints