URL
https://opencores.org/ocsvn/esoc/esoc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 41 |
Rev 49 |
| Line 15... |
Line 15... |
file delete $path_project_files/$path_script_files/esoc_control_test_stim.txt
|
file delete $path_project_files/$path_script_files/esoc_control_test_stim.txt
|
file delete $path_project_files/$path_script_files/esoc_rgmii_test_stim.txt
|
file delete $path_project_files/$path_script_files/esoc_rgmii_test_stim.txt
|
file copy $path_project_files/$path_script_files/esoc_control_test_stim_$4.txt $path_project_files/$path_script_files/esoc_control_test_stim.txt
|
file copy $path_project_files/$path_script_files/esoc_control_test_stim_$4.txt $path_project_files/$path_script_files/esoc_control_test_stim.txt
|
file copy $path_project_files/$path_script_files/esoc_rgmii_test_stim_$4.txt $path_project_files/$path_script_files/esoc_rgmii_test_stim.txt
|
file copy $path_project_files/$path_script_files/esoc_rgmii_test_stim_$4.txt $path_project_files/$path_script_files/esoc_rgmii_test_stim.txt
|
#
|
#
|
|
# copy memory init files for testbench
|
|
file delete $path_project_files/$path_msim_files/esoc_rom_2kx32.mif
|
|
file delete $path_project_files/$path_msim_files/esoc_ram_4kx1.mif
|
|
file copy $path_project_files/$path_design_files_altera/esoc_rom_nkx32/esoc_rom_2kx32.mif $path_project_files/$path_msim_files/esoc_rom_2kx32.mif
|
|
file copy $path_project_files/$path_design_files_altera/esoc_ram_nkx1/esoc_ram_4kx1.mif $path_project_files/$path_msim_files/esoc_ram_4kx1.mif
|
|
#
|
# rebuild IP
|
# rebuild IP
|
vcom -work work -2002 $path_project_files/$path_design_files_logixa/esoc_tb.vhd
|
vcom -work work -2002 $path_project_files/$path_design_files_logixa/esoc_tb.vhd
|
#
|
#
|
# restart modelsim
|
# restart modelsim
|
vsim -novopt -t ps work.esoc_tb
|
vsim -novopt -t ps work.esoc_tb
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.