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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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--
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---- Ethernet Switch on Configurable Logic IP Core ----
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-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.
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---- ----
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--
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---- This file is part of the ESoCL project ----
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-- Ease library : work
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---- http://www.opencores.org/cores/esoc/ ----
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-- HDL library : work
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---- ----
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-- Host name : S212065
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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-- User name : df768
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---- ----
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-- Time stamp : Tue Aug 19 08:05:18 2014
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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--
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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-- Designed by : L.Maarsen
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---- ----
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-- Company : LogiXA
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---- Author(s): L.Maarsen ----
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-- Project info : eSoC
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---- Bert Maarsen, lmaarsen@opencores.org ----
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--
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_search_engine_sa
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-- Object : Entity work.esoc_search_engine_sa
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-- Last modified : Mon Apr 14 12:50:09 2014.
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-- Last modified : Tue Aug 19 08:05:17 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee, std, work;
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library ieee, std, work;
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search_table_wren : out STD_LOGIC);
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search_table_wren : out STD_LOGIC);
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end entity esoc_search_engine_sa;
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end entity esoc_search_engine_sa;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_search_engine_sa.esoc_search_engine_sa
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-- Object : Architecture work.esoc_search_engine_sa.esoc_search_engine_sa
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-- Last modified : Mon Apr 14 12:50:09 2014.
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-- Last modified : Tue Aug 19 08:05:17 2014.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture esoc_search_engine_sa of esoc_search_engine_sa is
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architecture esoc_search_engine_sa of esoc_search_engine_sa is
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search_table_q(esoc_search_entry_mac+47 downto esoc_search_entry_mac) = search_key_i(esoc_search_entry_mac+47 downto esoc_search_entry_mac) and
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search_table_q(esoc_search_entry_mac+47 downto esoc_search_entry_mac) = search_key_i(esoc_search_entry_mac+47 downto esoc_search_entry_mac) and
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search_table_q(esoc_search_entry_valid) = '1' then
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search_table_q(esoc_search_entry_valid) = '1' then
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search_table_address_i <= std_logic_vector(to_unsigned(to_integer(unsigned(search_table_address_i))-1,search_table_address_i'length));
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search_table_address_i <= std_logic_vector(to_unsigned(to_integer(unsigned(search_table_address_i))-1,search_table_address_i'length));
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search_key_i(esoc_search_entry_valid) <= '1';
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search_key_i(esoc_search_entry_valid) <= '1';
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search_key_i(esoc_search_entry_update) <= '1';
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search_key_i(esoc_search_entry_aging) <= '1';
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search_table_wren <= '1';
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search_table_wren <= '1';
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search_state <= idle;
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search_state <= idle;
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-- there is no hit on SA and VID
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-- there is no hit on SA and VID
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else
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else
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Line 182... |
else
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else
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search_sa_drop_cnt <= '1';
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search_sa_drop_cnt <= '1';
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end if;
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end if;
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search_key_i(esoc_search_entry_valid) <= '1';
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search_key_i(esoc_search_entry_valid) <= '1';
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search_key_i(esoc_search_entry_update) <= '1';
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search_key_i(esoc_search_entry_aging) <= '1';
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search_state <= idle;
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search_state <= idle;
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end if;
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end if;
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end if;
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end if;
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when others => search_state <= idle;
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when others => search_state <= idle;
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Line 231... |
aging_state <= wait_empty;
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aging_state <= wait_empty;
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else
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else
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-- update the entry or even invalidate the entry
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-- update the entry or even invalidate the entry
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if search_table_q(esoc_search_entry_valid) = '1' then
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if search_table_q(esoc_search_entry_valid) = '1' then
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search_key_i <= search_table_q;
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search_key_i <= search_table_q;
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search_key_i(esoc_search_entry_valid) <= search_table_q(esoc_search_entry_update);
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search_key_i(esoc_search_entry_valid) <= search_table_q(esoc_search_entry_aging);
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search_key_i(esoc_search_entry_update) <= '0';
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search_key_i(esoc_search_entry_aging) <= '0';
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search_table_wren <= '1';
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search_table_wren <= '1';
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end if;
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end if;
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-- update address pointer to process next entry
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-- update address pointer to process next entry
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if aging_address = 2**search_table_address_i'length - 1 then
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if aging_address = 2**search_table_address_i'length - 1 then
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