| Line 1... |
Line 1... |
|
`timescale 1 ns/100ps
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// tb_top.v ////
|
//// tb_top.v ////
|
//// ////
|
//// ////
|
//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the Ethernet IP core project ////
|
| Line 37... |
Line 38... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
|
|
// no message
|
|
//
|
|
|
module tb_top (
|
module tb_top (
|
);
|
);
|
//******************************************************************************
|
//******************************************************************************
|
//internal signals
|
//internal signals
|
//******************************************************************************
|
//******************************************************************************
|
//system signals
|
//system signals
|
input Reset ,
|
reg Reset ;
|
input Clk_125M ,
|
reg Clk_125M ;
|
input Clk_user ,
|
reg Clk_user ;
|
input Clk_reg ,
|
reg Clk_reg ;
|
//user interface
|
//user interface
|
output Rx_mac_ra ,
|
wire Rx_mac_ra ;
|
input Rx_mac_rd ,
|
wire Rx_mac_rd ;
|
output [31:0] Rx_mac_data ,
|
wire [31:0] Rx_mac_data ;
|
output [1:0] Rx_mac_BE ,
|
wire [1:0] Rx_mac_BE ;
|
output Rx_mac_pa ,
|
wire Rx_mac_pa ;
|
output Rx_mac_sop ,
|
wire Rx_mac_sop ;
|
output Rx_mac_eop ,
|
wire Rx_mac_eop ;
|
//user interface
|
//user interface
|
output Tx_mac_wa ,
|
wire Tx_mac_wa ;
|
input Tx_mac_wr ,
|
wire Tx_mac_wr ;
|
input [31:0] Tx_mac_data ,
|
wire [31:0] Tx_mac_data ;
|
input [1:0] Tx_mac_BE ,//big endian
|
wire [1:0] Tx_mac_BE ;//big endian
|
input Tx_mac_sop ,
|
wire Tx_mac_sop ;
|
input Tx_mac_eop ,
|
wire Tx_mac_eop ;
|
//Phy interface
|
//Phy interface
|
//Phy interface
|
//Phy interface
|
output Gtx_clk ,//used only in GMII mode
|
wire Gtx_clk ;//used only in GMII mode
|
input Rx_clk ,
|
wire Rx_clk ;
|
input Tx_clk ,//used only in MII mode
|
wire Tx_clk ;//used only in MII mode
|
output Tx_er ,
|
wire Tx_er ;
|
output Tx_en ,
|
wire Tx_en ;
|
output [7:0] Txd ,
|
wire [7:0] Txd ;
|
input Rx_er ,
|
wire Rx_er ;
|
input Rx_dv ,
|
wire Rx_dv ;
|
input [7:0] Rxd ,
|
wire [7:0] Rxd ;
|
input Crs ,
|
wire Crs ;
|
input Col ,
|
wire Col ;
|
//Tx host interface
|
//Tx host interface
|
input [4:0] Tx_Hwmark ,
|
wire [4:0] Tx_Hwmark ;
|
input [4:0] Tx_Lwmark ,
|
wire [4:0] Tx_Lwmark ;
|
input pause_frame_send_en ,
|
wire pause_frame_send_en ;
|
input [15:0] pause_quanta_set ,
|
wire [15:0] pause_quanta_set ;
|
input MAC_tx_add_en ,
|
wire MAC_tx_add_en ;
|
input FullDuplex ,
|
wire FullDuplex ;
|
input [3:0] MaxRetry ,
|
wire [3:0] MaxRetry ;
|
input [5:0] IFGset ,
|
wire [5:0] IFGset ;
|
input [7:0] MAC_tx_add_prom_data ,
|
wire [7:0] MAC_tx_add_prom_data ;
|
input [2:0] MAC_tx_add_prom_add ,
|
wire [2:0] MAC_tx_add_prom_add ;
|
input MAC_tx_add_prom_wr ,
|
wire MAC_tx_add_prom_wr ;
|
input tx_pause_en ,
|
wire tx_pause_en ;
|
input xoff_cpu ,
|
wire xoff_cpu ;
|
input xon_cpu ,
|
wire xon_cpu ;
|
//Rx host interface
|
//Rx host interface
|
input MAC_rx_add_chk_en ,
|
wire MAC_rx_add_chk_en ;
|
input [7:0] MAC_rx_add_prom_data ,
|
wire [7:0] MAC_rx_add_prom_data ;
|
input [2:0] MAC_rx_add_prom_add ,
|
wire [2:0] MAC_rx_add_prom_add ;
|
input MAC_rx_add_prom_wr ,
|
wire MAC_rx_add_prom_wr ;
|
input broadcast_filter_en ,
|
wire broadcast_filter_en ;
|
input [15:0] broadcast_MAX ,
|
wire [15:0] broadcast_MAX ;
|
input RX_APPEND_CRC ,
|
wire RX_APPEND_CRC ;
|
input CRC_chk_en ,
|
wire CRC_chk_en ;
|
input [5:0] RX_IFG_SET ,
|
wire [5:0] RX_IFG_SET ;
|
input [15:0] RX_MAX_LENGTH ,// 1518
|
wire [15:0] RX_MAX_LENGTH ;// 1518
|
input [6:0] RX_MIN_LENGTH ,// 64
|
wire [6:0] RX_MIN_LENGTH ;// 64
|
//RMON host interface
|
//RMON host interface
|
input [5:0] CPU_rd_addr ,
|
wire [5:0] CPU_rd_addr ;
|
input CPU_rd_apply ,
|
wire CPU_rd_apply ;
|
output CPU_rd_grant ,
|
wire CPU_rd_grant ;
|
output [31:0] CPU_rd_dout ,
|
wire [31:0] CPU_rd_dout ;
|
//Phy int host interface
|
//Phy int host interface
|
input Line_loop_en ,
|
wire Line_loop_en ;
|
input [2:0] Speed ,
|
wire [2:0] Speed ;
|
//MII to CPU
|
//MII to CPU
|
input [7:0] Divider ,// Divider for the host clock
|
wire [7:0] Divider ;// Divider for the host clock
|
input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
|
wire [15:0] CtrlData ;// Control Data (to be written to the PHY reg.)
|
input [4:0] Rgad ,// Register Address (within the PHY)
|
wire [4:0] Rgad ;// Register Address (within the PHY)
|
input [4:0] Fiad ,// PHY Address
|
wire [4:0] Fiad ;// PHY Address
|
input NoPre ,// No Preamble (no 32-bit preamble)
|
wire NoPre ;// No Preamble (no 32-bit preamble)
|
input WCtrlData ,// Write Control Data operation
|
wire WCtrlData ;// Write Control Data operation
|
input RStat ,// Read Status operation
|
wire RStat ;// Read Status operation
|
input ScanStat ,// Scan Status operation
|
wire ScanStat ;// Scan Status operation
|
output Busy ,// Busy Signal
|
wire Busy ;// Busy Signal
|
output LinkFail ,// Link Integrity Signal
|
wire LinkFail ;// Link Integrity Signal
|
output Nvalid ,// Invalid Status (qualifier for the valid scan result)
|
wire Nvalid ;// Invalid Status (qualifier for the valid scan result)
|
output [15:0] Prsd ,// Read Status Data (data read from the PHY)
|
wire [15:0] Prsd ;// Read Status Data (data read from the PHY)
|
output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
|
wire WCtrlDataStart ;// This signals resets the WCTRLDATA bit in the MIIM Command register
|
output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
|
wire RStatStart ;// This signal resets the RSTAT BIT in the MIIM Command register
|
output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
|
wire UpdateMIIRX_DATAReg ;// Updates MII RX_DATA register with read data
|
//MII interface signals
|
//MII interface signals
|
inout Mdio ,// MII Management Data In
|
wire Mdio ;// MII Management Data In
|
output Mdc ,// MII Management Data Clock
|
wire Mdc ;// MII Management Data Clock
|
|
|
//******************************************************************************
|
//******************************************************************************
|
//internal signals
|
//internal signals
|
//******************************************************************************
|
//******************************************************************************
|
|
|
|
initial
|
|
begin
|
|
Reset =1;
|
|
#20 Reset =0;
|
|
end
|
|
always
|
|
begin
|
|
#4 Clk_125M=0;
|
|
#4 Clk_125M=1;
|
|
end
|
|
|
|
always
|
|
begin
|
|
#5 Clk_user=0;
|
|
#5 Clk_user=1;
|
|
end
|
|
|
|
always
|
|
begin
|
|
#10 Clk_reg=0;
|
|
#10 Clk_reg=1;
|
|
end
|
|
|
|
|
|
initial
|
|
begin
|
|
$shm_open("tb_top.shm",,900000000,);
|
|
$shm_probe("AS");
|
|
end
|
|
|
|
|
MAC_top U_MAC_top(
|
MAC_top U_MAC_top(
|
.//system signals (//system signals ),
|
//system signals (//system signals ),
|
.Reset (Reset ),
|
.Reset (Reset ),
|
.Clk_125M (Clk_125M ),
|
.Clk_125M (Clk_125M ),
|
.Clk_user (Clk_user ),
|
.Clk_user (Clk_user ),
|
.Clk_reg (Clk_reg ),
|
.Clk_reg (Clk_reg ),
|
.//user interface (//user interface ),
|
//user interface (//user interface ),
|
.Rx_mac_ra (Rx_mac_ra ),
|
.Rx_mac_ra (Rx_mac_ra ),
|
.Rx_mac_rd (Rx_mac_rd ),
|
.Rx_mac_rd (Rx_mac_rd ),
|
.Rx_mac_data (Rx_mac_data ),
|
.Rx_mac_data (Rx_mac_data ),
|
.Rx_mac_BE (Rx_mac_BE ),
|
.Rx_mac_BE (Rx_mac_BE ),
|
.Rx_mac_pa (Rx_mac_pa ),
|
.Rx_mac_pa (Rx_mac_pa ),
|
.Rx_mac_sop (Rx_mac_sop ),
|
.Rx_mac_sop (Rx_mac_sop ),
|
.Rx_mac_eop (Rx_mac_eop ),
|
.Rx_mac_eop (Rx_mac_eop ),
|
.//user interface (//user interface ),
|
//user interface (//user interface ),
|
.Tx_mac_wa (Tx_mac_wa ),
|
.Tx_mac_wa (Tx_mac_wa ),
|
.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_wr (Tx_mac_wr ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_data (Tx_mac_data ),
|
.Tx_mac_BE (Tx_mac_BE ),
|
.Tx_mac_BE (Tx_mac_BE ),
|
.Tx_mac_sop (Tx_mac_sop ),
|
.Tx_mac_sop (Tx_mac_sop ),
|
.Tx_mac_eop (Tx_mac_eop ),
|
.Tx_mac_eop (Tx_mac_eop ),
|
.//Phy interface (//Phy interface ),
|
//Phy interface (//Phy interface ),
|
.//Phy interface (//Phy interface ),
|
//Phy interface (//Phy interface ),
|
.Gtx_clk (Gtx_clk ),
|
.Gtx_clk (Gtx_clk ),
|
.Rx_clk (Rx_clk ),
|
.Rx_clk (Rx_clk ),
|
.Tx_clk (Tx_clk ),
|
.Tx_clk (Tx_clk ),
|
.Tx_er (Tx_er ),
|
.Tx_er (Tx_er ),
|
.Tx_en (Tx_en ),
|
.Tx_en (Tx_en ),
|
| Line 169... |
Line 204... |
.Rx_er (Rx_er ),
|
.Rx_er (Rx_er ),
|
.Rx_dv (Rx_dv ),
|
.Rx_dv (Rx_dv ),
|
.Rxd (Rxd ),
|
.Rxd (Rxd ),
|
.Crs (Crs ),
|
.Crs (Crs ),
|
.Col (Col ),
|
.Col (Col ),
|
.//Tx host interface (//Tx host interface ),
|
//Tx host interface (//Tx host interface ),
|
.Tx_Hwmark (Tx_Hwmark ),
|
.Tx_Hwmark (Tx_Hwmark ),
|
.Tx_Lwmark (Tx_Lwmark ),
|
.Tx_Lwmark (Tx_Lwmark ),
|
.pause_frame_send_en (pause_frame_send_en ),
|
.pause_frame_send_en (pause_frame_send_en ),
|
.pause_quanta_set (pause_quanta_set ),
|
.pause_quanta_set (pause_quanta_set ),
|
.MAC_tx_add_en (MAC_tx_add_en ),
|
.MAC_tx_add_en (MAC_tx_add_en ),
|
| Line 184... |
Line 219... |
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
|
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
|
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
|
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
|
.tx_pause_en (tx_pause_en ),
|
.tx_pause_en (tx_pause_en ),
|
.xoff_cpu (xoff_cpu ),
|
.xoff_cpu (xoff_cpu ),
|
.xon_cpu (xon_cpu ),
|
.xon_cpu (xon_cpu ),
|
.//Rx host interface (//Rx host interface ),
|
//Rx host interface (//Rx host interface ),
|
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
|
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
|
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
|
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
|
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
|
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
|
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
|
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
|
.broadcast_filter_en (broadcast_filter_en ),
|
.broadcast_filter_en (broadcast_filter_en ),
|
| Line 196... |
Line 231... |
.RX_APPEND_CRC (RX_APPEND_CRC ),
|
.RX_APPEND_CRC (RX_APPEND_CRC ),
|
.CRC_chk_en (CRC_chk_en ),
|
.CRC_chk_en (CRC_chk_en ),
|
.RX_IFG_SET (RX_IFG_SET ),
|
.RX_IFG_SET (RX_IFG_SET ),
|
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
|
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
|
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
|
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
|
.//RMON host interface (//RMON host interface ),
|
//RMON host interface (//RMON host interface ),
|
.CPU_rd_addr (CPU_rd_addr ),
|
.CPU_rd_addr (CPU_rd_addr ),
|
.CPU_rd_apply (CPU_rd_apply ),
|
.CPU_rd_apply (CPU_rd_apply ),
|
.CPU_rd_grant (CPU_rd_grant ),
|
.CPU_rd_grant (CPU_rd_grant ),
|
.CPU_rd_dout (CPU_rd_dout ),
|
.CPU_rd_dout (CPU_rd_dout ),
|
.//Phy int host interface (//Phy int host interface ),
|
//Phy int host interface (//Phy int host interface ),
|
.Line_loop_en (Line_loop_en ),
|
.Line_loop_en (Line_loop_en ),
|
.Speed (Speed ),
|
.Speed (Speed ),
|
.//MII to CPU (//MII to CPU ),
|
//MII to CPU (//MII to CPU ),
|
.Divider (Divider ),
|
.Divider (Divider ),
|
.CtrlData (CtrlData ),
|
.CtrlData (CtrlData ),
|
.Rgad (Rgad ),
|
.Rgad (Rgad ),
|
.Fiad (Fiad ),
|
.Fiad (Fiad ),
|
.NoPre (NoPre ),
|
.NoPre (NoPre ),
|
| Line 220... |
Line 255... |
.Nvalid (Nvalid ),
|
.Nvalid (Nvalid ),
|
.Prsd (Prsd ),
|
.Prsd (Prsd ),
|
.WCtrlDataStart (WCtrlDataStart ),
|
.WCtrlDataStart (WCtrlDataStart ),
|
.RStatStart (RStatStart ),
|
.RStatStart (RStatStart ),
|
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
|
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
|
.//MII interface signals (//MII interface signals ),
|
//MII interface signals (//MII interface signals ),
|
.Mdio (Mdio ),
|
.Mdio (Mdio ),
|
.Mdc (Mdc )
|
.Mdc (Mdc )
|
|
);
|
|
|
|
Phy_sim U_Phy_sim (
|
|
.Gtx_clk (Gtx_clk ),
|
|
.Rx_clk (Rx_clk ),
|
|
.Tx_clk (Tx_clk ),
|
|
.Tx_er (Tx_er ),
|
|
.Tx_en (Tx_en ),
|
|
.Txd (Txd ),
|
|
.Rx_er (Rx_er ),
|
|
.Rx_dv (Rx_dv ),
|
|
.Rxd (Rxd ),
|
|
.Crs (Crs ),
|
|
.Col (Col ),
|
|
.Speed (Speed )
|
|
);
|
|
|
|
User_int_sim U_User_int_sim(
|
|
.Reset (Reset ),
|
|
.Clk_user (Clk_user ),
|
|
//user inputerface (//user inputerface ),
|
|
.Rx_mac_ra (Rx_mac_ra ),
|
|
.Rx_mac_rd (Rx_mac_rd ),
|
|
.Rx_mac_data (Rx_mac_data ),
|
|
.Rx_mac_BE (Rx_mac_BE ),
|
|
.Rx_mac_pa (Rx_mac_pa ),
|
|
.Rx_mac_sop (Rx_mac_sop ),
|
|
.Rx_mac_eop (Rx_mac_eop ),
|
|
//user inputerface (//user inputerface ),
|
|
.Tx_mac_wa (Tx_mac_wa ),
|
|
.Tx_mac_wr (Tx_mac_wr ),
|
|
.Tx_mac_data (Tx_mac_data ),
|
|
.Tx_mac_BE (Tx_mac_BE ),
|
|
.Tx_mac_sop (Tx_mac_sop ),
|
|
.Tx_mac_eop (Tx_mac_eop )
|
|
);
|
|
|
|
reg_int_sim U_reg_int_sim(
|
|
.Reset (Reset ),
|
|
.Clk_reg (Clk_reg ),
|
|
//Tx host interface (//Tx host interface ),
|
|
.Tx_Hwmark (Tx_Hwmark ),
|
|
.Tx_Lwmark (Tx_Lwmark ),
|
|
.pause_frame_send_en (pause_frame_send_en ),
|
|
.pause_quanta_set (pause_quanta_set ),
|
|
.MAC_tx_add_en (MAC_tx_add_en ),
|
|
.FullDuplex (FullDuplex ),
|
|
.MaxRetry (MaxRetry ),
|
|
.IFGset (IFGset ),
|
|
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
|
|
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
|
|
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
|
|
.tx_pause_en (tx_pause_en ),
|
|
.xoff_cpu (xoff_cpu ),
|
|
.xon_cpu (xon_cpu ),
|
|
//Rx host interface (//Rx host interface ),
|
|
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
|
|
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
|
|
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
|
|
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
|
|
.broadcast_filter_en (broadcast_filter_en ),
|
|
.broadcast_MAX (broadcast_MAX ),
|
|
.RX_APPEND_CRC (RX_APPEND_CRC ),
|
|
.CRC_chk_en (CRC_chk_en ),
|
|
.RX_IFG_SET (RX_IFG_SET ),
|
|
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
|
|
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
|
|
//RMON host interface (//RMON host interface ),
|
|
.CPU_rd_addr (CPU_rd_addr ),
|
|
.CPU_rd_apply (CPU_rd_apply ),
|
|
.CPU_rd_grant (CPU_rd_grant ),
|
|
.CPU_rd_dout (CPU_rd_dout ),
|
|
//Phy int host interface (//Phy int host interface ),
|
|
.Line_loop_en (Line_loop_en ),
|
|
.Speed (Speed ),
|
|
//MII to CPU (//MII to CPU ),
|
|
.Divider (Divider ),
|
|
.CtrlData (CtrlData ),
|
|
.Rgad (Rgad ),
|
|
.Fiad (Fiad ),
|
|
.NoPre (NoPre ),
|
|
.WCtrlData (WCtrlData ),
|
|
.RStat (RStat ),
|
|
.ScanStat (ScanStat ),
|
|
.Busy (Busy ),
|
|
.LinkFail (LinkFail ),
|
|
.Nvalid (Nvalid ),
|
|
.Prsd (Prsd ),
|
|
.WCtrlDataStart (WCtrlDataStart ),
|
|
.RStatStart (RStatStart ),
|
|
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
|
);
|
);
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
