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Line 37... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2005/12/16 06:44:17 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.2 2005/12/13 12:15:38 Administrator
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// no message
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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// no message
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//
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//
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Line 205... |
reg[7:0] pause_counter ;
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reg[7:0] pause_counter ;
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reg pause_quanta_sub ;
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reg pause_quanta_sub ;
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reg pause_frame_send_en_dl1 ;
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reg pause_frame_send_en_dl1 ;
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reg[15:0] pause_quanta_set_dl1 ;
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reg[15:0] pause_quanta_set_dl1 ;
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reg [4:0] send_pause_frame_counter ;
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reg [4:0] send_pause_frame_counter ;
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reg xoff_gen_reg ;
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reg xon_gen_reg ;
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reg xoff_gen_complete ;
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reg xoff_gen_complete ;
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reg xon_gen_complete ;
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reg xon_gen_complete ;
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//******************************************************************************
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//******************************************************************************
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//boundery signal processing
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//boundery signal processing
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//******************************************************************************
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//******************************************************************************
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Line 221... |
else
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else
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begin
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begin
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pause_frame_send_en_dl1 <=pause_frame_send_en ;
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pause_frame_send_en_dl1 <=pause_frame_send_en ;
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pause_quanta_set_dl1 <=pause_quanta_set ;
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pause_quanta_set_dl1 <=pause_quanta_set ;
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end
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end
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//******************************************************************************
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//******************************************************************************
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//state machine
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//state machine
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//******************************************************************************
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//******************************************************************************
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assign Collision=TxEn&CRS;
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assign Collision=TxEn&CRS;
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| Line 280... |
Line 283... |
StateIdle:
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StateIdle:
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if (!FullDuplex&&CRS)
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if (!FullDuplex&&CRS)
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Next_state=StateDefer;
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Next_state=StateDefer;
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else if (pause_apply)
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else if (pause_apply)
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Next_state=StatePause;
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Next_state=StatePause;
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else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)))
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else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
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Next_state=StatePreamble;
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Next_state=StatePreamble;
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else
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else
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Next_state=Current_state;
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Next_state=Current_state;
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StatePause:
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StatePause:
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if (pause_counter==512/8)
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if (pause_counter==512/8)
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| Line 299... |
Line 302... |
else
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else
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Next_state=Current_state;
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Next_state=Current_state;
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StateSFD:
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StateSFD:
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if (!FullDuplex&&Collision)
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if (!FullDuplex&&Collision)
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Next_state=StateJam;
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Next_state=StateJam;
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else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
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else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
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Next_state=StateSendPauseFrame;
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Next_state=StateSendPauseFrame;
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else
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else
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Next_state=StateData;
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Next_state=StateData;
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StateSendPauseFrame:
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StateSendPauseFrame:
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if (send_pause_frame_counter==19)
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if (send_pause_frame_counter==19)
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| Line 341... |
Line 344... |
else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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StateFCS:
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StateFCS:
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if (!FullDuplex&&Collision)
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if (!FullDuplex&&Collision)
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Next_state =StateJam;
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Next_state =StateJam;
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else if (pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg))
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else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
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Next_state =StateDefer;
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Next_state =StateDefer;
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else if (CRC_end)
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else if (CRC_end)
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Next_state =StateSwitchNext;
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Next_state =StateSwitchNext;
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else
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else
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Next_state =Current_state;
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Next_state =Current_state;
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| Line 438... |
Line 441... |
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//MAC_rx_FF
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//MAC_rx_FF
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//data have one cycle delay after fifo read signals
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//data have one cycle delay after fifo read signals
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always @ (*)
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always @ (*)
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if (Current_state==StateData ||
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if (Current_state==StateData ||
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Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen_reg||xon_gen_reg)) ||
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Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) ||
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Current_state==StateJamDrop&&PktDrpEvenPtr||
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Current_state==StateJamDrop&&PktDrpEvenPtr||
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Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
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Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
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Fifo_rd =1;
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Fifo_rd =1;
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else
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else
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Fifo_rd =0;
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Fifo_rd =0;
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| Line 459... |
Line 462... |
else
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else
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Fifo_rd_retry =0;
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Fifo_rd_retry =0;
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//RMII
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//RMII
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always @(Current_state)
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always @(Current_state)
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if (Current_state==StatePreamble||Current_state==StateSFD||
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if (Current_state==StatePreamble||Current_state==StateSFD||
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Current_state==StateData||
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Current_state==StateData||Current_state==StateSendPauseFrame||
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Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
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Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
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TxEn_tmp =1;
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TxEn_tmp =1;
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else
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else
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TxEn_tmp =0;
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TxEn_tmp =0;
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Line 575... |
else if (Current_state==StateSendPauseFrame)
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else if (Current_state==StateSendPauseFrame)
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Tx_pkt_type_rmon <=3'b100;
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Tx_pkt_type_rmon <=3'b100;
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else if(MAC_header_slot)
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else if(MAC_header_slot)
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Tx_pkt_type_rmon <={1'b0,TxD_tmp};
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Tx_pkt_type_rmon <={1'b0,TxD_tmp};
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always @(Tx_pkt_length_rmon)
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always @(Tx_pkt_length_rmon)
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if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
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if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
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Src_MAC_ptr =1;
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Src_MAC_ptr =1;
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else
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else
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Src_MAC_ptr =0;
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Src_MAC_ptr =0;
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//MAC_tx_addr_add
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//MAC_tx_addr_add
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always @ (Tx_pkt_length_rmon or Fifo_rd or Src_MAC_ptr)
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always @ (posedge Clk or posedge Reset)
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if (Src_MAC_ptr&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
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if (Reset)
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MAC_tx_addr_rd =1;
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MAC_tx_addr_rd <=0;
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else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
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MAC_tx_addr_rd <=1;
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else
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else
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MAC_tx_addr_rd =0;
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MAC_tx_addr_rd <=0;
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always @ (Tx_pkt_length_rmon or Fifo_rd)
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always @ (Tx_pkt_length_rmon or Fifo_rd)
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if ((Tx_pkt_length_rmon==5)&&Fifo_rd)
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if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
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MAC_tx_addr_init=1;
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MAC_tx_addr_init=1;
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else
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else
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MAC_tx_addr_init=0;
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MAC_tx_addr_init=0;
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//flow control
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//flow control
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Line 609... |
pause_quanta_sub <=0;
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pause_quanta_sub <=0;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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xoff_gen_reg <=0;
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xon_gen_reg <=0;
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end
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else if (Current_state==StateDefer)
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begin
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xoff_gen_reg <=xoff_gen;
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xon_gen_reg <=xon_gen;
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end
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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xoff_gen_complete <=0;
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xoff_gen_complete <=0;
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else if(Current_state==StateDefer&&xoff_gen_reg)
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else if(Current_state==StateDefer&&xoff_gen)
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xoff_gen_complete <=1;
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xoff_gen_complete <=1;
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else
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else
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xoff_gen_complete <=0;
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xoff_gen_complete <=0;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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xon_gen_complete <=0;
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xon_gen_complete <=0;
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else if(Current_state==StateDefer&&xon_gen_reg)
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else if(Current_state==StateDefer&&xon_gen)
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xon_gen_complete <=1;
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xon_gen_complete <=1;
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else
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else
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xon_gen_complete <=0;
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xon_gen_complete <=0;
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endmodule
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endmodule
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