URL https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [bench/] [verilog/] [Phy_sim.v] - Diff between revs 7 and 23

Rev 7	Rev 23
Line 37...	Line 37...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2006/01/19 14:07:50 maverickist`
	`// verification is complete.`
	`//`
`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`	`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
`// no message`	`// no message`
`//`	`//`

`timescale 1ns/100ps	`timescale 1ns/100ps
Line 67...	Line 70...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`// internal signals`	`// internal signals`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`reg Clk_25m ;//used for 100 Mbps mode`	`reg Clk_25m ;//used for 100 Mbps mode`
`reg Clk_2_5m ;//used for 10 Mbps mode`	`reg Clk_2_5m ;//used for 10 Mbps mode`
`wire Rx_clk ;`	`//wire Rx_clk ;`
`wire Tx_clk ;//used only in MII mode`	`//wire Tx_clk ;//used only in MII mode`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`always`	`always`
`begin`	`begin`
`#20 Clk_25m=0;`	`#20 Clk_25m=0;`
`#20 Clk_25m=1;`	`#20 Clk_25m=1;`