URL https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [bench/] [verilog/] [User_int_sim.v] - Diff between revs 6 and 7

Rev 6	Rev 7
Line 36...	Line 36...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2005/12/13 12:15:35 Administrator`
	`// no message`
`//`	`//`
`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`	`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
`// no message`	`// no message`
`//`	`//`
`module User_int_sim (`	`module User_int_sim (`
`input Reset ,`	`input Reset ,`
`input Clk_user ,`	`input Clk_user ,`
	`input CPU_init_end ,`
`//user inputerface`	`//user inputerface`
`input Rx_mac_ra ,`	`input Rx_mac_ra ,`
`output Rx_mac_rd ,`	`output Rx_mac_rd ,`
`input [31:0] Rx_mac_data ,`	`input [31:0] Rx_mac_data ,`
`input [1:0] Rx_mac_BE ,`	`input [1:0] Rx_mac_BE ,`
Line 85...	Line 89...
`else if (Tx_mac_wa)`	`else if (Tx_mac_wa)`
`Start_tran <=1;`	`Start_tran <=1;`


`always @ (posedge Clk_user )`	`always @ (posedge Clk_user )`
`if (Tx_mac_wa)`	`if (Tx_mac_wa&&CPU_init_end)`
`$ip_32W_gen("config.ini",operation,data);`	`$ip_32W_gen("../data/config.ini",operation,data);`
`else`	`else`
`begin`	`begin`
`operation <=0;`	`operation <=0;`
`data <=0;`	`data <=0;`
`end`	`end`