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https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2006/01/19 14:07:51 maverickist
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// verification is complete.
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//
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// replaced tab with space.
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// replaced tab with space.
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// passed 9.6k length frame test.
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// passed 9.6k length frame test.
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//
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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wire [7:0] CA ;
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wire [7:0] CA ;
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//Phy int host interface
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//Phy int host interface
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wire Line_loop_en ;
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wire Line_loop_en ;
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wire [2:0] Speed ;
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wire [2:0] Speed ;
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//mii
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//mii
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wire Mdio ;// MII Management Data In
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wire Mdo ;// MII Management Data out
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wire Mdi ;// MII Management Data In
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wire MdoEn ;// MII Management Data out enable
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wire Mdc ;// MII Management Data Clock
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wire Mdc ;// MII Management Data Clock
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wire CPU_init_end ;
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wire CPU_init_end ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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.WRB (WRB ),
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.WRB (WRB ),
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.CD_in (CD_in ),
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.CD_in (CD_in ),
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.CD_out (CD_out ),
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.CD_out (CD_out ),
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.CA (CA ),
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.CA (CA ),
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//MII interface signals (//MII interface signals ),
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//MII interface signals (//MII interface signals ),
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.Mdio (Mdio ),
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.Mdi (Mdi ),
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.Mdo (Mdo ),
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.MdoEn (MdoEn ),
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.Mdc (Mdc )
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.Mdc (Mdc )
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);
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);
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Phy_sim U_Phy_sim (
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Phy_sim U_Phy_sim (
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.Gtx_clk (Gtx_clk ),
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.Gtx_clk (Gtx_clk ),
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