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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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// no message
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//
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//
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module tb_top (
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module tb_top (
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| Line 80... |
Line 84... |
wire Rx_er ;
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wire Rx_er ;
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wire Rx_dv ;
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wire Rx_dv ;
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wire [7:0] Rxd ;
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wire [7:0] Rxd ;
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wire Crs ;
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wire Crs ;
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wire Col ;
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wire Col ;
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//Tx host interface
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wire CSB ;
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wire [4:0] Tx_Hwmark ;
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wire WRB ;
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wire [4:0] Tx_Lwmark ;
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wire [15:0] CD_in ;
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wire pause_frame_send_en ;
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wire [15:0] CD_out ;
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wire [15:0] pause_quanta_set ;
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wire [7:0] CA ;
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wire MAC_tx_add_en ;
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wire FullDuplex ;
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wire [3:0] MaxRetry ;
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wire [5:0] IFGset ;
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wire [7:0] MAC_tx_add_prom_data ;
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wire [2:0] MAC_tx_add_prom_add ;
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wire MAC_tx_add_prom_wr ;
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wire tx_pause_en ;
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wire xoff_cpu ;
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wire xon_cpu ;
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//Rx host interface
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wire MAC_rx_add_chk_en ;
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wire [7:0] MAC_rx_add_prom_data ;
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wire [2:0] MAC_rx_add_prom_add ;
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wire MAC_rx_add_prom_wr ;
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wire broadcast_filter_en ;
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wire [15:0] broadcast_MAX ;
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wire RX_APPEND_CRC ;
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wire CRC_chk_en ;
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wire [5:0] RX_IFG_SET ;
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wire [15:0] RX_MAX_LENGTH ;// 1518
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wire [6:0] RX_MIN_LENGTH ;// 64
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//RMON host interface
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wire [5:0] CPU_rd_addr ;
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wire CPU_rd_apply ;
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wire CPU_rd_grant ;
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wire [31:0] CPU_rd_dout ;
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//Phy int host interface
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//Phy int host interface
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wire Line_loop_en ;
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wire Line_loop_en ;
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wire [2:0] Speed ;
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wire [2:0] Speed ;
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//MII to CPU
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//mii
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wire [7:0] Divider ;// Divider for the host clock
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wire [15:0] CtrlData ;// Control Data (to be written to the PHY reg.)
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wire [4:0] Rgad ;// Register Address (within the PHY)
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wire [4:0] Fiad ;// PHY Address
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wire NoPre ;// No Preamble (no 32-bit preamble)
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wire WCtrlData ;// Write Control Data operation
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wire RStat ;// Read Status operation
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wire ScanStat ;// Scan Status operation
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wire Busy ;// Busy Signal
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wire LinkFail ;// Link Integrity Signal
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wire Nvalid ;// Invalid Status (qualifier for the valid scan result)
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wire [15:0] Prsd ;// Read Status Data (data read from the PHY)
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wire WCtrlDataStart ;// This signals resets the WCTRLDATA bit in the MIIM Command register
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wire RStatStart ;// This signal resets the RSTAT BIT in the MIIM Command register
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wire UpdateMIIRX_DATAReg ;// Updates MII RX_DATA register with read data
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//MII interface signals
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wire Mdio ;// MII Management Data In
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wire Mdio ;// MII Management Data In
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wire Mdc ;// MII Management Data Clock
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wire Mdc ;// MII Management Data Clock
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wire CPU_init_end ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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initial
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initial
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| Line 176... |
Line 137... |
//system signals (//system signals ),
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//system signals (//system signals ),
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.Reset (Reset ),
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.Reset (Reset ),
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.Clk_125M (Clk_125M ),
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.Clk_125M (Clk_125M ),
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.Clk_user (Clk_user ),
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.Clk_user (Clk_user ),
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.Clk_reg (Clk_reg ),
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.Clk_reg (Clk_reg ),
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.Speed (Speed ),
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//user interface (//user interface ),
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//user interface (//user interface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_BE (Rx_mac_BE ),
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| Line 204... |
Line 166... |
.Rx_er (Rx_er ),
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.Rx_er (Rx_er ),
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.Rx_dv (Rx_dv ),
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.Rx_dv (Rx_dv ),
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.Rxd (Rxd ),
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.Rxd (Rxd ),
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.Crs (Crs ),
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.Crs (Crs ),
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.Col (Col ),
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.Col (Col ),
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//Tx host interface (//Tx host interface ),
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//host interface
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.Tx_Hwmark (Tx_Hwmark ),
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.CSB (CSB ),
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.Tx_Lwmark (Tx_Lwmark ),
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.WRB (WRB ),
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.pause_frame_send_en (pause_frame_send_en ),
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.CD_in (CD_in ),
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.pause_quanta_set (pause_quanta_set ),
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.CD_out (CD_out ),
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.MAC_tx_add_en (MAC_tx_add_en ),
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.CA (CA ),
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.FullDuplex (FullDuplex ),
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.MaxRetry (MaxRetry ),
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.IFGset (IFGset ),
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.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
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.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
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.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
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.tx_pause_en (tx_pause_en ),
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.xoff_cpu (xoff_cpu ),
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.xon_cpu (xon_cpu ),
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//Rx host interface (//Rx host interface ),
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.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
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.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
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.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
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.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
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.broadcast_filter_en (broadcast_filter_en ),
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.broadcast_MAX (broadcast_MAX ),
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.RX_APPEND_CRC (RX_APPEND_CRC ),
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.CRC_chk_en (CRC_chk_en ),
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.RX_IFG_SET (RX_IFG_SET ),
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.RX_MAX_LENGTH (RX_MAX_LENGTH ),
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.RX_MIN_LENGTH (RX_MIN_LENGTH ),
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//RMON host interface (//RMON host interface ),
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.CPU_rd_addr (CPU_rd_addr ),
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.CPU_rd_apply (CPU_rd_apply ),
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.CPU_rd_grant (CPU_rd_grant ),
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.CPU_rd_dout (CPU_rd_dout ),
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//Phy int host interface (//Phy int host interface ),
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.Line_loop_en (Line_loop_en ),
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.Speed (Speed ),
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//MII to CPU (//MII to CPU ),
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.Divider (Divider ),
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.CtrlData (CtrlData ),
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.Rgad (Rgad ),
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.Fiad (Fiad ),
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.NoPre (NoPre ),
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.WCtrlData (WCtrlData ),
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.RStat (RStat ),
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.ScanStat (ScanStat ),
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.Busy (Busy ),
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.LinkFail (LinkFail ),
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.Nvalid (Nvalid ),
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.Prsd (Prsd ),
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.WCtrlDataStart (WCtrlDataStart ),
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.RStatStart (RStatStart ),
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.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
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//MII interface signals (//MII interface signals ),
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//MII interface signals (//MII interface signals ),
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.Mdio (Mdio ),
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.Mdio (Mdio ),
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.Mdc (Mdc )
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.Mdc (Mdc )
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);
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);
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| Line 278... |
Line 195... |
);
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);
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User_int_sim U_User_int_sim(
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User_int_sim U_User_int_sim(
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.Reset (Reset ),
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.Reset (Reset ),
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.Clk_user (Clk_user ),
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.Clk_user (Clk_user ),
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.CPU_init_end (CPU_init_end ),
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//user inputerface (//user inputerface ),
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//user inputerface (//user inputerface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_BE (Rx_mac_BE ),
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| Line 295... |
Line 213... |
.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_eop (Tx_mac_eop )
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.Tx_mac_eop (Tx_mac_eop )
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);
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);
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reg_int_sim U_reg_int_sim(
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host_sim U_host_sim(
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.Reset (Reset ),
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.Reset (Reset ),
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.Clk_reg (Clk_reg ),
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.Clk_reg (Clk_reg ),
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//Tx host interface (//Tx host interface ),
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.CSB (CSB ),
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.Tx_Hwmark (Tx_Hwmark ),
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.WRB (WRB ),
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.Tx_Lwmark (Tx_Lwmark ),
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.CD_in (CD_in ),
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.pause_frame_send_en (pause_frame_send_en ),
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.CD_out (CD_out ),
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.pause_quanta_set (pause_quanta_set ),
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.CPU_init_end (CPU_init_end ),
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.MAC_tx_add_en (MAC_tx_add_en ),
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.CA (CA )
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.FullDuplex (FullDuplex ),
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.MaxRetry (MaxRetry ),
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.IFGset (IFGset ),
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.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
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.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
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.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
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.tx_pause_en (tx_pause_en ),
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.xoff_cpu (xoff_cpu ),
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.xon_cpu (xon_cpu ),
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//Rx host interface (//Rx host interface ),
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.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
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.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
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.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
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.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
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.broadcast_filter_en (broadcast_filter_en ),
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.broadcast_MAX (broadcast_MAX ),
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.RX_APPEND_CRC (RX_APPEND_CRC ),
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.CRC_chk_en (CRC_chk_en ),
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.RX_IFG_SET (RX_IFG_SET ),
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.RX_MAX_LENGTH (RX_MAX_LENGTH ),
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.RX_MIN_LENGTH (RX_MIN_LENGTH ),
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//RMON host interface (//RMON host interface ),
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.CPU_rd_addr (CPU_rd_addr ),
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.CPU_rd_apply (CPU_rd_apply ),
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.CPU_rd_grant (CPU_rd_grant ),
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.CPU_rd_dout (CPU_rd_dout ),
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//Phy int host interface (//Phy int host interface ),
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.Line_loop_en (Line_loop_en ),
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.Speed (Speed ),
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//MII to CPU (//MII to CPU ),
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.Divider (Divider ),
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.CtrlData (CtrlData ),
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.Rgad (Rgad ),
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.Fiad (Fiad ),
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.NoPre (NoPre ),
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.WCtrlData (WCtrlData ),
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.RStat (RStat ),
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.ScanStat (ScanStat ),
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.Busy (Busy ),
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.LinkFail (LinkFail ),
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.Nvalid (Nvalid ),
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.Prsd (Prsd ),
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.WCtrlDataStart (WCtrlDataStart ),
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.RStatStart (RStatStart ),
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.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
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);
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);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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