URL
https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 5 |
Rev 6 |
Line 37... |
Line 37... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
|
|
// no message
|
|
//
|
|
|
module Clk_ctrl(
|
module Clk_ctrl(
|
Reset ,
|
Reset ,
|
Clk_125M ,
|
Clk_125M ,
|
//host interface,
|
//host interface,
|
Line 80... |
Line 83... |
//******************************************************************************
|
//******************************************************************************
|
assign Gtx_clk =Clk_125M ;
|
assign Gtx_clk =Clk_125M ;
|
assign MAC_rx_clk =Rx_clk ;
|
assign MAC_rx_clk =Rx_clk ;
|
|
|
CLK_DIV2 U_0_CLK_DIV2(
|
CLK_DIV2 U_0_CLK_DIV2(
|
|
.Reset (Reset ),
|
.IN (Rx_clk ),
|
.IN (Rx_clk ),
|
.OUT (Rx_clk_div2 )
|
.OUT (Rx_clk_div2 )
|
);
|
);
|
|
|
CLK_DIV2 U_1_CLK_DIV2(
|
CLK_DIV2 U_1_CLK_DIV2(
|
|
.Reset (Reset ),
|
.IN (Tx_clk ),
|
.IN (Tx_clk ),
|
.OUT (Tx_clk_div2 )
|
.OUT (Tx_clk_div2 )
|
);
|
);
|
|
|
CLK_SWITCH U_0_CLK_SWITCH(
|
CLK_SWITCH U_0_CLK_SWITCH(
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.