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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2008/08/17 11:41:30 maverickist
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// no message
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//
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// Revision 1.5 2006/06/25 04:58:56 maverickist
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// Revision 1.5 2006/06/25 04:58:56 maverickist
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// no message
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// no message
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//
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//
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// Revision 1.4 2006/05/28 05:09:20 maverickist
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// Revision 1.4 2006/05/28 05:09:20 maverickist
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// no message
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// no message
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parameter SYS_pause =3'd1;
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parameter SYS_pause =3'd1;
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parameter SYS_wait_end =3'd2;
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parameter SYS_wait_end =3'd2;
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parameter SYS_idle =3'd3;
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parameter SYS_idle =3'd3;
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parameter FF_emtpy_err =3'd4;
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parameter FF_emtpy_err =3'd4;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_wr;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_ungray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_reg;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_rd;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_pl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_pl1;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
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reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_ungray;
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reg [`MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
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reg [35:0] Din;
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reg [35:0] Din;
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reg [35:0] Din_tmp;
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reg [35:0] Din_tmp;
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reg [35:0] Din_tmp_reg;
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reg [35:0] Din_tmp_reg;
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wire[35:0] Dout;
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wire[35:0] Dout;
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reg Wr_en;
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reg Wr_en;
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reg Wr_en_tmp;
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reg Wr_en_tmp;
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reg Wr_en_ptr;
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reg Wr_en_ptr;
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wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
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wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse4;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
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wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse3;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
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wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse2;
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wire[`MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
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reg Full;
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reg Full;
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reg Almost_full;
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reg Almost_full;
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reg Empty /* synthesis syn_keep=1 */;
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reg Empty /* synthesis syn_keep=1 */;
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reg [3:0] Current_state /* synthesis syn_keep=1 */;
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reg [3:0] Current_state /* synthesis syn_keep=1 */;
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reg [3:0] Next_state;
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reg [3:0] Next_state;
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