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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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//
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module MAC_rx_FF (
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module MAC_rx_FF (
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Reset ,
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Reset ,
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Clk_MAC ,
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Clk_MAC ,
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Clk_SYS ,
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Clk_SYS ,
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Line 142... |
reg Packet_number_sub ;
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reg Packet_number_sub ;
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wire Packet_number_add_edge;
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wire Packet_number_add_edge;
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reg Packet_number_add_dl1;
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reg Packet_number_add_dl1;
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reg Packet_number_add_dl2;
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reg Packet_number_add_dl2;
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reg Packet_number_add ;
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reg Packet_number_add ;
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reg Packet_number_add_tmp ;
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reg Packet_number_add_tmp_dl1;
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reg Packet_number_add_tmp_dl2;
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reg Rx_mac_sop_tmp_dl1;
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reg Rx_mac_sop_tmp_dl1;
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reg[35:0] Dout_dl1;
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reg[35:0] Dout_dl1;
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reg[1:0] Rx_mac_BE ;
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reg[1:0] Rx_mac_BE ;
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//******************************************************************************
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//******************************************************************************
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Line 314... |
if (Reset)
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if (Reset)
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Fifo_data_byte1 <=0;
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Fifo_data_byte1 <=0;
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else if (Current_state==State_byte1&&Fifo_data_en_dl1)
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else if (Current_state==State_byte1&&Fifo_data_en_dl1)
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Fifo_data_byte1 <=Fifo_data_dl1;
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Fifo_data_byte1 <=Fifo_data_dl1;
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always @ (posedge Clk_MAC or posedge Reset)
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always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 )
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if (Reset)
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Fifo_data_byte0 <=0;
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else if (Current_state==State_byte0&&Fifo_data_en_dl1)
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Fifo_data_byte0 <=Fifo_data_dl1;
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always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 or Fifo_data_byte0 )
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case (Current_state)
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case (Current_state)
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State_be0:
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State_be0:
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Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
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Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
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State_be1:
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State_be1:
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Din ={4'b1001,Fifo_data_byte3,24'h0};
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Din ={4'b1001,Fifo_data_byte3,24'h0};
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State_be2:
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State_be2:
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Din ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
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Din ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
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State_be3:
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State_be3:
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Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
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Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
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default:
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default:
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Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
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Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
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endcase
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endcase
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always @ (Current_state or Fifo_data_en)
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always @ (Current_state or Fifo_data_en)
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if (Current_state==State_be0||Current_state==State_be1||
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if (Current_state==State_be0||Current_state==State_be1||
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Current_state==State_be2||Current_state==State_be3||
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Current_state==State_be2||Current_state==State_be3||
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Line 338... |
else
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else
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Wr_en <=0;
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Wr_en <=0;
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//this signal for read side to handle the packet number in fifo
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//this signal for read side to handle the packet number in fifo
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always @ (posedge Clk_MAC or posedge Reset)
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always @ (posedge Clk_MAC or posedge Reset)
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if (Reset)
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if (Reset)
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Packet_number_add <=0;
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Packet_number_add_tmp <=0;
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else if (Current_state==State_be0||Current_state==State_be1||
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else if (Current_state==State_be0||Current_state==State_be1||
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Current_state==State_be2||Current_state==State_be3)
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Current_state==State_be2||Current_state==State_be3)
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Packet_number_add_tmp <=1;
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else
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Packet_number_add_tmp <=0;
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always @ (posedge Clk_MAC or posedge Reset)
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if (Reset)
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begin
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Packet_number_add_tmp_dl1 <=0;
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Packet_number_add_tmp_dl2 <=0;
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end
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else
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begin
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Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
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Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
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end
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//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
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//expand to two cycles long almost=16 ns
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//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
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always @ (posedge Clk_MAC or posedge Reset)
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if (Reset)
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Packet_number_add <=0;
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else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
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Packet_number_add <=1;
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Packet_number_add <=1;
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else
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else
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Packet_number_add <=0;
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Packet_number_add <=0;
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