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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MAC_rx_add_chk.v ////
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//// MAC_rx_add_chk.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2005/12/16 06:44:17 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
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// no message
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// no message
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//
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//
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module MAC_rx_add_chk (
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module MAC_rx_add_chk (
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input MAC_add_prom_wr ;
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input MAC_add_prom_wr ;
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//******************************************************************************
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//******************************************************************************
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//internal signals
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//internal signals
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//******************************************************************************
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//******************************************************************************
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reg[2:0] addra;
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reg [2:0] addr_rd;
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wire[2:0] addrb;
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wire[2:0] addr_wr;
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wire[7:0] dinb;
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wire[7:0] din;
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wire[7:0] douta;
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wire[7:0] dout;
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wire web;
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wire wr_en;
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reg MAC_rx_add_chk_err;
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reg MAC_rx_add_chk_err;
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reg MAC_add_prom_wr_dl1;
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reg MAC_add_prom_wr_dl1;
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reg MAC_add_prom_wr_dl2;
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reg MAC_add_prom_wr_dl2;
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reg [7:0] data_dl1 ;
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reg MAC_add_en_dl1 ;
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//******************************************************************************
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//******************************************************************************
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//write data from cpu to prom
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//write data from cpu to prom
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//******************************************************************************
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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begin
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begin
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data_dl1 <=0;
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MAC_add_en_dl1 <=0;
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end
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else
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begin
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data_dl1 <=data;
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MAC_add_en_dl1 <=MAC_add_en;
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end
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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begin
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MAC_add_prom_wr_dl1 <=0;
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MAC_add_prom_wr_dl1 <=0;
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MAC_add_prom_wr_dl2 <=0;
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MAC_add_prom_wr_dl2 <=0;
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end
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end
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else
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else
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begin
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begin
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MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
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MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
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MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
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MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
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end
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end
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assign web =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
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assign addrb =MAC_add_prom_add;
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assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
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assign dinb =MAC_add_prom_data;
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assign addr_wr =MAC_add_prom_add;
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assign din =MAC_add_prom_data;
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//******************************************************************************
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//******************************************************************************
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//mac add verify
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//mac add verify
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//******************************************************************************
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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addra <=0;
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addr_rd <=0;
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else if (Init)
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else if (Init)
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addra <=0;
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addr_rd <=0;
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else if (MAC_add_en)
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else if (MAC_add_en)
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addra <=addra + 1;
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addr_rd <=addr_rd + 1;
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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if (Reset)
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if (Reset)
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MAC_rx_add_chk_err <=0;
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MAC_rx_add_chk_err <=0;
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else if (Init)
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else if (Init)
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MAC_rx_add_chk_err <=0;
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MAC_rx_add_chk_err <=0;
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else if (MAC_rx_add_chk_en&&MAC_add_en&&douta!=data)
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else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1)
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MAC_rx_add_chk_err <=1;
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MAC_rx_add_chk_err <=1;
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//******************************************************************************
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//******************************************************************************
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//a port for read ,b port for write .
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//a port for read ,b port for write .
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//******************************************************************************
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//******************************************************************************
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duram #(8,3,"M512","DUAL_PORT") U_duram(
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duram #(8,3,"M512","DUAL_PORT") U_duram(
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.data_a (dinb ),
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.data_a (din ),
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.wren_a (web ),
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.wren_a (wr_en ),
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.address_a (addra ),
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.address_a (addr_wr ),
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.address_b (addrb ),
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.address_b (addr_rd ),
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.clock_a (Clk ),
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.clock_a (Clk ),
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.clock_b (Clk ),
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.clock_b (Clk ),
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.q_b (douta ));
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.q_b (dout ));
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endmodule
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endmodule
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No newline at end of file
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