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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_ctrl.v] - Diff between revs 7 and 19

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Rev 7 Rev 19
Line 37... Line 37...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//                                                                    
//                                                                    
// CVS Revision History                                               
// CVS Revision History                                               
//                                                                    
//                                                                    
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2006/01/19 14:07:54  maverickist
 
// verification is complete.
 
//
// Revision 1.3  2005/12/16 06:44:17  Administrator
// Revision 1.3  2005/12/16 06:44:17  Administrator
// replaced tab with space.
// replaced tab with space.
// passed 9.6k length frame test.
// passed 9.6k length frame test.
//
//
// Revision 1.2  2005/12/13 12:15:37  Administrator
// Revision 1.2  2005/12/13 12:15:37  Administrator
Line 160... Line 163...
reg             Fifo_data_end;
reg             Fifo_data_end;
reg             Fifo_data_err;
reg             Fifo_data_err;
reg             CRC_en;
reg             CRC_en;
reg             CRC_init;
reg             CRC_init;
reg             Rx_apply_rmon;
reg             Rx_apply_rmon;
 
reg             Rx_apply_rmon_tmp;
 
reg             Rx_apply_rmon_tmp_pl1;
reg [2:0]       Rx_pkt_err_type_rmon;
reg [2:0]       Rx_pkt_err_type_rmon;
reg             MAC_add_en;
reg             MAC_add_en;
reg [2:0]       Rx_pkt_type_rmon;
reg [2:0]       Rx_pkt_type_rmon;
reg [7:0]       pause_quanta_h      ;
reg [7:0]       pause_quanta_h      ;
reg [15:0]      pause_quanta        ;
reg [15:0]      pause_quanta        ;
Line 264... Line 269...
                    else
                    else
                        Next_state  =Current_state;
                        Next_state  =Current_state;
            State_FFFullErrEnd:
            State_FFFullErrEnd:
                        Next_state  =State_FFFullDrop;
                        Next_state  =State_FFFullDrop;
            State_IFG:
            State_IFG:
                    if (IFG_counter==RX_IFG_SET)
                    if (IFG_counter==RX_IFG_SET-4)   //remove some additional time     
                        Next_state  =State_idle;
                        Next_state  =State_idle;
                    else
                    else
                        Next_state  =Current_state;
                        Next_state  =Current_state;
 
 
            default:
            default:
Line 331... Line 336...
    if (Reset)
    if (Reset)
        Frame_length_counter        <=0;
        Frame_length_counter        <=0;
    else if (Current_state==State_SFD)
    else if (Current_state==State_SFD)
        Frame_length_counter        <=1;
        Frame_length_counter        <=1;
    else if (Current_state==State_data)
    else if (Current_state==State_data)
        Frame_length_counter        <=Frame_length_counter+ 1;
        Frame_length_counter        <=Frame_length_counter+ 1'b1;
 
 
always @ (Frame_length_counter or RX_MIN_LENGTH)
always @ (Frame_length_counter or RX_MIN_LENGTH)
    if (Frame_length_counter<RX_MIN_LENGTH)
    if (Frame_length_counter<RX_MIN_LENGTH)
        Too_short   =1;
        Too_short   =1;
    else
    else
Line 345... Line 350...
    if (Frame_length_counter>RX_MAX_LENGTH)
    if (Frame_length_counter>RX_MAX_LENGTH)
        Too_long    =1;
        Too_long    =1;
    else
    else
        Too_long    =0;
        Too_long    =0;
 
 
assign Rx_pkt_length_rmon=Frame_length_counter;
assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;
 
 
 
always @ (posedge Clk or posedge Reset)
 
    if (Reset)
 
        Rx_apply_rmon_tmp   <=0;
 
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
 
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
 
        Rx_apply_rmon_tmp   <=1;
 
    else
 
        Rx_apply_rmon_tmp   <=0;
 
 
 
always @ (posedge Clk or posedge Reset)
 
    if (Reset)
 
        Rx_apply_rmon_tmp_pl1   <=0;
 
    else
 
        Rx_apply_rmon_tmp_pl1   <=Rx_apply_rmon_tmp;
 
 
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
    if (Reset)
    if (Reset)
        Rx_apply_rmon   <=0;
        Rx_apply_rmon   <=0;
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon   <=1;
        Rx_apply_rmon   <=1;
    else
    else if (Rx_apply_rmon_tmp_pl1)
        Rx_apply_rmon   <=0;
        Rx_apply_rmon   <=0;
 
 
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
    if (Reset)
    if (Reset)
        Rx_pkt_err_type_rmon    <=0;
        Rx_pkt_err_type_rmon    <=0;

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