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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Diff between revs 5 and 6

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Rev 5	Rev 6
Line 37...	Line 37...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2005/12/13 12:15:36 Administrator`
	`// no message`
	`//`
	`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
	`// no message`
	`//`

`module Phy_int (`	`module Phy_int (`
`Reset ,`	`Reset ,`
`MAC_rx_clk ,`	`MAC_rx_clk ,`
`MAC_tx_clk ,`	`MAC_tx_clk ,`
Line 100...	Line 106...
`reg [7:0] Txd ;`	`reg [7:0] Txd ;`
`reg MCrs_dv ;`	`reg MCrs_dv ;`
`reg [7:0] MRxD ;`	`reg [7:0] MRxD ;`
`reg Rx_er_dl1 ;`	`reg Rx_er_dl1 ;`
`reg Rx_dv_dl1 ;`	`reg Rx_dv_dl1 ;`
	`reg Rx_dv_dl2 ;`
`reg [7:0] Rxd_dl1 ;`	`reg [7:0] Rxd_dl1 ;`
`reg [7:0] Rxd_dl2 ;`	`reg [7:0] Rxd_dl2 ;`
`reg Crs_dl1 ;`	`reg Crs_dl1 ;`
`reg Col_dl1 ;`	`reg Col_dl1 ;`
`//******************************************************************************`	`//******************************************************************************`
Line 145...	Line 152...

`always @ (posedge MAC_tx_clk or posedge Reset)`	`always @ (posedge MAC_tx_clk or posedge Reset)`
`if (Reset)`	`if (Reset)`
`Tx_en <=0;`	`Tx_en <=0;`
`else if(MTxEn_dl1)`	`else if(MTxEn_dl1)`
`Tx_en <=MTxEn_dl1;`	`Tx_en <=1;`
	`else`
	`Tx_en <=0;`

`assign Tx_er=0;`	`assign Tx_er=0;`

`//******************************************************************************`	`//******************************************************************************`
`//Rx control`	`//Rx control`
Line 158...	Line 167...
`always @ (posedge MAC_rx_clk or posedge Reset)`	`always @ (posedge MAC_rx_clk or posedge Reset)`
`if (Reset)`	`if (Reset)`
`begin`	`begin`
`Rx_er_dl1 <=0;`	`Rx_er_dl1 <=0;`
`Rx_dv_dl1 <=0;`	`Rx_dv_dl1 <=0;`
	`Rx_dv_dl2 <=0 ;`
`Rxd_dl1 <=0;`	`Rxd_dl1 <=0;`
`Rxd_dl2 <=0;`	`Rxd_dl2 <=0;`
`Crs_dl1 <=0;`	`Crs_dl1 <=0;`
`Col_dl1 <=0;`	`Col_dl1 <=0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`Rx_er_dl1 <=Rx_er ;`	`Rx_er_dl1 <=Rx_er ;`
`Rx_dv_dl1 <=Rx_dv ;`	`Rx_dv_dl1 <=Rx_dv ;`
	`Rx_dv_dl2 <=Rx_dv_dl1 ;`
`Rxd_dl1 <=Rxd ;`	`Rxd_dl1 <=Rxd ;`
`Rxd_dl2 <=Rxd_dl1 ;`	`Rxd_dl2 <=Rxd_dl1 ;`
`Crs_dl1 <=Crs ;`	`Crs_dl1 <=Crs ;`
`Col_dl1 <=Col ;`	`Col_dl1 <=Col ;`
`end`	`end`



`assign MRxErr =Rx_er_dl1 ;`	`assign MRxErr =Rx_er_dl1 ;`
`assign MCRS =Crs_dl1 ;`	`assign MCRS =Crs_dl1 ;`

`always @ (posedge MAC_rx_clk or posedge Reset)`	`always @ (posedge MAC_rx_clk or posedge Reset)`
`if (Reset)`	`if (Reset)`
`MCrs_dv <=0;`	`MCrs_dv <=0;`
`else if(Line_loop_en)`	`else if(Line_loop_en)`
`MCrs_dv <=Tx_en;`	`MCrs_dv <=Tx_en;`
`else if(Rx_dv_dl1)`	`else if(Rx_dv_dl2)`
`MCrs_dv <=1;`	`MCrs_dv <=1;`
`else`	`else`
`MCrs_dv <=0;`	`MCrs_dv <=0;`

`always @ (posedge MAC_rx_clk or posedge Reset)`	`always @ (posedge MAC_rx_clk or posedge Reset)`
Line 201...	Line 210...
`always @ (posedge MAC_rx_clk or posedge Reset)`	`always @ (posedge MAC_rx_clk or posedge Reset)`
`if (Reset)`	`if (Reset)`
`MRxD <=0;`	`MRxD <=0;`
`else if(Line_loop_en)`	`else if(Line_loop_en)`
`MRxD <=Txd;`	`MRxD <=Txd;`
`else if(Speed[2]&&Rx_dv_dl1)`	`else if(Speed[2]&&Rx_dv_dl2)`
`MRxD <=Rxd_dl1;`	`MRxD <=Rxd_dl2;`
`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`	`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`	`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`


`endmodule`	`endmodule`
`No newline at end of file`	`No newline at end of file`

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Diff between revs 5 and 6