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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Diff between revs 6 and 7

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Rev 6	Rev 7
Line 37...	Line 37...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2005/12/16 06:44:14 Administrator`
	`// replaced tab with space.`
	`// passed 9.6k length frame test.`
	`//`
`// Revision 1.2 2005/12/13 12:15:36 Administrator`	`// Revision 1.2 2005/12/13 12:15:36 Administrator`
`// no message`	`// no message`
`//`	`//`
`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`	`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
`// no message`	`// no message`
Line 215...	Line 219...
`else if(Speed[2]&&Rx_dv_dl2)`	`else if(Speed[2]&&Rx_dv_dl2)`
`MRxD <=Rxd_dl2;`	`MRxD <=Rxd_dl2;`
`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`	`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`	`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`


`endmodule`	`endmodule`
`No newline at end of file`	`No newline at end of file`

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