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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [TECH/] [CLK_DIV2.v] - Diff between revs 5 and 6

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//////////////////////////////////////////////////////////////////////
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//                                                                    
//                                                                    
// CVS Revision History                                               
// CVS Revision History                                               
//                                                                    
//                                                                    
// $Log: not supported by cvs2svn $ 
// $Log: not supported by cvs2svn $ 
 
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
 
// no message
 
// 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// This file can only used for simulation .
// You need to replace it with your own element according to technology
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module CLK_DIV2 (
module CLK_DIV2 (
 
input           Reset,
input           IN,
input           IN,
output  reg     OUT
output  reg     OUT
);
);
 
 
always @ (posedge IN)
always @ (posedge IN or posedge Reset)
 
        if (Reset)
 
                OUT             <=0;
 
        else
        OUT             <=!OUT;
        OUT             <=!OUT;
 
 
endmodule
endmodule
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