| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2006/01/19 14:07:53 maverickist
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// verification is complete.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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// no message
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//
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//
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// Revision 1.4 2005/08/16 12:07:57 Administrator
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// Revision 1.4 2005/08/16 12:07:57 Administrator
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// no message
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// no message
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| Line 105... |
Line 108... |
Rgad,
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Rgad,
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Fiad,
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Fiad,
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WCtrlData,
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WCtrlData,
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RStat,
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RStat,
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ScanStat,
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ScanStat,
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Mdio,
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Mdo,
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MdoEn,
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Mdi,
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Mdc,
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Mdc,
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Busy,
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Busy,
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Prsd,
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Prsd,
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LinkFail,
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LinkFail,
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Nvalid,
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Nvalid,
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| Line 128... |
Line 133... |
input [4:0] Fiad; // PHY Address
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input [4:0] Fiad; // PHY Address
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input NoPre; // No Preamble (no 32-bit preamble)
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input NoPre; // No Preamble (no 32-bit preamble)
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input WCtrlData; // Write Control Data operation
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input WCtrlData; // Write Control Data operation
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input RStat; // Read Status operation
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input RStat; // Read Status operation
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input ScanStat; // Scan Status operation
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input ScanStat; // Scan Status operation
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inout Mdio; // MII Management Data In
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output Mdo; // MII Management Data Output
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output MdoEn; // MII Management Data Output Enable
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input Mdi;
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output Mdc; // MII Management Data Clock
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output Mdc; // MII Management Data Clock
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output Busy; // Busy Signal
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output Busy; // Busy Signal
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output LinkFail; // Link Integrity Signal
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output LinkFail; // Link Integrity Signal
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| Line 197... |
Line 204... |
reg LatchByte0_d;
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reg LatchByte0_d;
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reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
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reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
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reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
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wire Mdo; // MII Management Data Output
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wire MdoEn; // MII Management Data Output Enable
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wire Mdi;
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assign Mdi=Mdio;
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assign Mdio=MdoEn?Mdo:1'bz;
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/*
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assign Mdi=Mdio;
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assign Mdio=MdoEn?Mdo:1'bz;
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*/
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// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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// Generation of the EndBusy signal. It is used for ending the MII Management operation.
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always @ (posedge Clk or posedge Reset)
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always @ (posedge Clk or posedge Reset)
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