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Line 57... |
input LinkFail ,// Link Integrity Signal
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input LinkFail ,// Link Integrity Signal
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input Nvalid ,// Invalid Status (qualifier for the valid scan result)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input [15:0] Prsd ,// Read Status Data (data read from the PHY)
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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input UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data
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);
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);
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RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
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