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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [reg_int.v] - Diff between revs 23 and 28

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Rev 23	Rev 28
Line 138...	Line 138...
`7'd32: CD_out<=CPU_rd_dout[31:16] ;`	`7'd32: CD_out<=CPU_rd_dout[31:16] ;`
`7'd33: CD_out<=Line_loop_en ;`	`7'd33: CD_out<=Line_loop_en ;`
`7'd34: CD_out<=Speed ;`	`7'd34: CD_out<=Speed ;`
`default: CD_out<=0 ;`	`default: CD_out<=0 ;`
`endcase`	`endcase`
`else`
`CD_out<=0 ;`

`endmodule`	`endmodule`

`module RegCPUData(`	`module RegCPUData(`
`RegOut,`	`RegOut,`

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