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#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version Synplify Pro 8.1
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#-- Version Synplify 8.1
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#-- Project file D:\root\home\primitive\primitive_tri_mode_mac(NA)\syn\syn.prj
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#-- Project file D:\root\home\ethernet_tri_mode\syn\syn.prj
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#-- Written on Mon Dec 05 14:10:50 2005
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#-- Written on Thu Jan 19 20:25:55 2006
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#add_file options
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#add_file options
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add_file -verilog "../rtl/verilog/header.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
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add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
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add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
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add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
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add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
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add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
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add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
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add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
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add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
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add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
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add_file -verilog "../cores/afifo.v"
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add_file -verilog "../rtl/verilog/TECH/duram.v"
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add_file -verilog "../cores/duram.v"
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add_file -verilog "../rtl/verilog/RMON.v"
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add_file -verilog "../rtl/verilog/RMON.v"
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add_file -verilog "../rtl/verilog/MAC_rx.v"
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add_file -verilog "../rtl/verilog/MAC_rx.v"
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add_file -verilog "../rtl/verilog/MAC_tx.v"
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add_file -verilog "../rtl/verilog/MAC_tx.v"
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add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
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add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
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add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
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add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
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add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v"
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add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v"
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add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v"
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add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v"
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add_file -verilog "../rtl/verilog/eth_miim.v"
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add_file -verilog "../rtl/verilog/eth_miim.v"
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add_file -verilog "../rtl/verilog/Clk_ctrl.v"
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add_file -verilog "../rtl/verilog/Clk_ctrl.v"
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add_file -verilog "../rtl/verilog/Phy_int.v"
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add_file -verilog "../rtl/verilog/Phy_int.v"
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add_file -verilog "../rtl/verilog/Reg_int.v"
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add_file -verilog "../rtl/verilog/MAC_top.v"
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add_file -verilog "../rtl/verilog/MAC_top.v"
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#implementation: "syn"
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#implementation: "syn"
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impl -add syn
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impl -add syn
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#simulation options
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#simulation options
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set_option -write_verilog 1
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set_option -write_verilog 1
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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#VIF options
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set_option -write_vif 0
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 0
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set_option -write_apr_constraint 0
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#set result format/file last
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#set result format/file last
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project -result_file "./MAC_top.vqm"
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project -result_file "./MAC_top.vqm"
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