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#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version Synplify Pro 8.1
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#-- Version Synplify Pro 8.1
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#-- Project file D:\root\home\ethernet_tri_mode\syn\syn_xilinx.prj
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#-- Project file D:\root\home\jon\ethernet_tri_mode\syn\syn_xilinx.prj
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#-- Written on Sun Jun 25 09:43:29 2006
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#-- Written on Mon Aug 04 17:11:28 2008
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#add_file options
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#add_file options
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add_file -verilog "../rtl/verilog/header.v"
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add_file -verilog "../rtl/verilog/header.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
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add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
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add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_SWITCH.v"
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add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_SWITCH.v"
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add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_DIV2.v"
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add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_DIV2.v"
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add_file -verilog "../rtl/verilog/eth_miim.v"
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add_file -verilog "../rtl/verilog/eth_miim.v"
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add_file -verilog "../rtl/verilog/Clk_ctrl.v"
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add_file -verilog "../rtl/verilog/Clk_ctrl.v"
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add_file -verilog "../rtl/verilog/Phy_int.v"
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add_file -verilog "../rtl/verilog/Phy_int.v"
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add_file -verilog "../rtl/verilog/afifo.v"
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add_file -verilog "../rtl/verilog/Reg_int.v"
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add_file -verilog "../rtl/verilog/Reg_int.v"
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add_file -verilog "../rtl/verilog/MAC_top.v"
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add_file -verilog "../rtl/verilog/MAC_top.v"
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#implementation: "syn"
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#implementation: "syn"
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#map options
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#map options
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set_option -frequency auto
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set_option -frequency auto
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set_option -run_prop_extract 0
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set_option -run_prop_extract 0
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set_option -fanout_limit 10000
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set_option -fanout_limit 10000
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 1
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set_option -pipe 1
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set_option -pipe 1
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -verification_mode 0
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set_option -verification_mode 0
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set_option -fixgatedclocks 0
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set_option -fixgatedclocks 0
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set_option -modular 0
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set_option -modular 0
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