URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 209 |
Rev 254 |
Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.9 2002/10/09 13:16:51 tadejm
|
|
// Just back-up; not completed testbench and some testcases are not
|
|
// wotking properly yet.
|
|
//
|
// Revision 1.8 2002/09/13 18:41:45 mohor
|
// Revision 1.8 2002/09/13 18:41:45 mohor
|
// Rearanged testcases
|
// Rearanged testcases
|
//
|
//
|
// Revision 1.7 2002/09/13 12:29:14 mohor
|
// Revision 1.7 2002/09/13 12:29:14 mohor
|
// Headers changed.
|
// Headers changed.
|
Line 203... |
Line 207... |
/* MII Status Register */
|
/* MII Status Register */
|
`define ETH_MIISTATUS_LINKFAIL 0 /* Link Fail bit */
|
`define ETH_MIISTATUS_LINKFAIL 0 /* Link Fail bit */
|
`define ETH_MIISTATUS_BUSY 1 /* MII Busy bit */
|
`define ETH_MIISTATUS_BUSY 1 /* MII Busy bit */
|
`define ETH_MIISTATUS_NVALID 2 /* Data in MII Status Register is invalid bit */
|
`define ETH_MIISTATUS_NVALID 2 /* Data in MII Status Register is invalid bit */
|
|
|
|
/* TX Control Register */
|
|
`define ETH_TX_CTRL_TXPAUSERQ 32'h10000 /* Send PAUSE request */
|
|
|
|
|
`define TIME $display(" Time: %0t", $time)
|
`define TIME $display(" Time: %0t", $time)
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.