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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 297 and 302

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_defines.v] - Diff between revs 297 and 302

Rev 297	Rev 302
Line 39...	Line 39...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.31 2003/08/14 16:42:58 simons`
	`// Artisan ram instance added.`
	`//`
`// Revision 1.30 2003/06/13 11:55:37 mohor`	`// Revision 1.30 2003/06/13 11:55:37 mohor`
`// Define file in eth_cop.v is changed to eth_defines.v. Some defines were`	`// Define file in eth_cop.v is changed to eth_defines.v. Some defines were`
`// moved from tb_eth_defines.v to eth_defines.v.`	`// moved from tb_eth_defines.v to eth_defines.v.`
`//`	`//`
`// Revision 1.29 2002/11/19 18:13:49 mohor`	`// Revision 1.29 2002/11/19 18:13:49 mohor`
Line 166...	Line 169...



//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS	//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS

	`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus

`// Ethernet implemented in Xilinx Chips`	`// Ethernet implemented in Xilinx Chips`
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo	// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors	// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
`// Core is going to be implemented in Virtex FPGA and contains Virtex`	`// Core is going to be implemented in Virtex FPGA and contains Virtex`