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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// Revision 1.2 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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`include "timescale.v"
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`include "timescale.v"
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module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
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module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
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RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,
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RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
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TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
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TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
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TxUsedDataOutDetected, Pause, ReceivedPauseFrm
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TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
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LoadRxStatus, SetPauseTimer
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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Line 92... |
input RxStartFrm;
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input RxStartFrm;
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input RxEndFrm;
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input RxEndFrm;
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input RxFlow;
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input RxFlow;
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input ReceiveEnd;
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input ReceiveEnd;
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input [47:0]MAC;
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input [47:0]MAC;
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input PassAll;
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input DlyCrcEn;
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input DlyCrcEn;
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input TxDoneIn;
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input TxDoneIn;
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input TxAbortIn;
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input TxAbortIn;
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input TxStartFrmOut;
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input TxStartFrmOut;
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input ReceivedLengthOK;
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input ReceivedLengthOK;
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input ReceivedPacketGood;
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input ReceivedPacketGood;
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input TxUsedDataOutDetected;
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input TxUsedDataOutDetected;
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input LoadRxStatus;
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output Pause;
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output Pause;
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output ReceivedPauseFrm;
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output ReceivedPauseFrm;
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output AddressOK;
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output SetPauseTimer;
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reg Pause;
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reg Pause;
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reg AddressOK; // Multicast or unicast address detected
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reg AddressOK; // Multicast or unicast address detected
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reg TypeLengthOK; // Type/Length field contains 0x8808
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reg TypeLengthOK; // Type/Length field contains 0x8808
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reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
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reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
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wire ByteCntEq14; // ByteCnt = 14
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wire ByteCntEq14; // ByteCnt = 14
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wire ByteCntEq15; // ByteCnt = 15
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wire ByteCntEq15; // ByteCnt = 15
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wire ByteCntEq16; // ByteCnt = 16
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wire ByteCntEq16; // ByteCnt = 16
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wire ByteCntEq17; // ByteCnt = 17
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wire ByteCntEq17; // ByteCnt = 17
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wire ByteCntEq18; // ByteCnt = 18
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wire ByteCntEq18; // ByteCnt = 18
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wire SetPauseTimer; //
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wire DecrementPauseTimer; //
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wire DecrementPauseTimer; //
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wire PauseTimerEq0; //
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wire PauseTimerEq0; //
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wire ResetSlotTimer; //
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wire ResetSlotTimer; //
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wire IncrementSlotTimer; //
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wire IncrementSlotTimer; //
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wire SlotFinished; //
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wire SlotFinished; //
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Line 274... |
always @ (posedge MRxClk or posedge RxReset )
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always @ (posedge MRxClk or posedge RxReset )
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begin
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begin
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if(RxReset)
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if(RxReset)
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LatchedTimerValue[15:0] <= #Tp 16'h0;
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LatchedTimerValue[15:0] <= #Tp 16'h0;
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else
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else
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if(~PassAll & DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
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if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
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LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
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LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
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else
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else
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if(ReceiveEnd)
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if(ReceiveEnd)
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LatchedTimerValue[15:0] <= #Tp 16'h0;
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LatchedTimerValue[15:0] <= #Tp 16'h0;
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end
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end
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Line 422... |
ReceivedPauseFrm <=#Tp 1'b0;
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ReceivedPauseFrm <=#Tp 1'b0;
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else
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else
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
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if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
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ReceivedPauseFrm <=#Tp 1'b1;
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ReceivedPauseFrm <=#Tp 1'b1;
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else
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else
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if(ReceiveEnd)
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if(RxStartFrm)
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ReceivedPauseFrm <=#Tp 1'b0;
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ReceivedPauseFrm <=#Tp 1'b0;
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end
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end
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endmodule
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endmodule
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